diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2017-09-20 10:05:51 +0800 |
|---|---|---|
| committer | Elaine Zhang <zhangqing@rock-chips.com> | 2017-09-20 10:29:37 +0800 |
| commit | a8cf408589711612dd69cda6d3effb086830df8f (patch) | |
| tree | 4b4a56b208ef8efe1b5bcc8f849db5cd503eae74 | |
| parent | 1b523997b38e6b1fe8212d46d5be131bac73d025 (diff) | |
ARM64: dts: rockchip: rk3399: assigned clk_uart4_src parent to PPLL
clk_uart4_src default parent is 24M,does not satisfy the
fractional divider must set that denominator is 20 times
larger than numerator.
Change-Id: I21fd9866794e052414a6fdf1d64840ac2a0bb8f2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi index 9c2212515c44..14ff440843cb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi @@ -75,8 +75,8 @@ }; &uart4 { - assigned-clocks = <&cru SCLK_UART_SRC>; - assigned-clock-parents = <&cru PLL_GPLL>; + assigned-clocks = <&pmucru SCLK_UART4_SRC>; + assigned-clock-parents = <&pmucru PLL_PPLL>; }; &spdif { |