diff options
author | David Wu <david.wu@rock-chips.com> | 2018-03-08 11:49:48 +0800 |
---|---|---|
committer | Tao Huang <huangtao@rock-chips.com> | 2018-03-08 15:09:24 +0800 |
commit | 97648a4ce7fbf4b3c0b3842de95859346d037294 (patch) | |
tree | d9a8b32f1dd64fe40d5cd654af868c35f3463ce4 | |
parent | 3efb6d37bdfb2321525a50886854002ed843ee3b (diff) |
arm64: dts: rockchip: px30: Add 12ma strength for rmii mac_refclk pin
If the mac_refclk is provided from mac controller, the pin of mac_refclk
needs to setup 12ma strength, or the signal is not good.
If the mac_refclk is provided from phy, the pin of mac_refclk needs not
to setup 12ma strength, the phy would do it.
Change-Id: I4f6e6d081b4616363d10358c9e36d71cacbdb134
Signed-off-by: David Wu <david.wu@rock-chips.com>
-rw-r--r-- | arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts | 2 | ||||
-rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 14 |
3 files changed, 15 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts index 78ae50b9a02f..fa2f5dc8c760 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr3-v10.dts @@ -298,6 +298,8 @@ assigned-clocks = <&cru SCLK_GMAC>; assigned-clock-parents = <&gmac_clkin>; clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk>; snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 50000 50000>; diff --git a/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts b/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts index 3d38e0713e28..656b26757e9b 100644 --- a/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts +++ b/arch/arm64/boot/dts/rockchip/px30-evb-ddr4-v10.dts @@ -298,6 +298,8 @@ assigned-clocks = <&cru SCLK_GMAC>; assigned-clock-parents = <&gmac_clkin>; clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk>; snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 50000 50000>; diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 74ef00065fcc..d7e25bb525f2 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -976,7 +976,7 @@ "pclk_mac", "clk_mac_speed"; phy-mode = "rmii"; pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; + pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; resets = <&cru SRST_GMAC_A>; reset-names = "stmmaceth"; power-domains = <&power PX30_PD_GMAC>; @@ -2504,8 +2504,16 @@ /* mac_mdio */ <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>, /* mac_mdc */ - <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>, - /* mac_clk */ + <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + }; + + mac_refclk_12ma: mac-refclk-12ma { + rockchip,pins = + <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + + mac_refclk: mac-refclk { + rockchip,pins = <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; }; }; |