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| author | Romain Perier <romain.perier@collabora.com> | 2017-09-04 10:51:19 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-10-24 15:25:27 +0200 |
| commit | 6f8c539313d884f4715b328e1ce4a3987649b97e (patch) | |
| tree | d1b701bd908b8c5ac156f7cbbec0e81a545927bb | |
| parent | c1cf6e1a20b79dc29f05ece99f4c1d219af1eb6c (diff) | |
arm64: dts: rockchip: add efuse for RK3368 SoCsv4.15-rockchip-dts64-2
This adds the definition for eFuse that is found on RK3368 SoCs with the
corresponding data cells.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3368.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index e0518b4bc6c2..fffcc61e1c89 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -854,6 +854,22 @@ status = "disabled"; }; + efuse256: efuse@ffb00000 { + compatible = "rockchip,rk3368-efuse"; + reg = <0x0 0xffb00000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + temp_adjust: temp-adjust@1f { + reg = <0x1f 0x1>; + }; + }; + gic: interrupt-controller@ffb71000 { compatible = "arm,gic-400"; interrupt-controller; |