diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2018-12-12 11:08:54 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-12-12 15:03:25 +0800 |
| commit | 4604ed7218fecddba41772e4ca82179c968cc565 (patch) | |
| tree | 4b4145cbef591e5a571849aaa45ed446d4f1fb44 | |
| parent | b5eac72e73dc12c2ebdfde009ff8e7f8540e9eb9 (diff) | |
clk: rockchip: rk3399: export SCLK_I2SOUT_SRC clk ID for i2s
Change-Id: Ifbcea830e5f49946c1feea3f51d125e6ed566d5f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3399.c | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3399-cru.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index d1ddf7a97dcb..2aececc12b8e 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -714,7 +714,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT, RK3399_CLKGATE_CON(8), 11, GFLAGS), - MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, + MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(31), 0, 2, MFLAGS), COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(31), 2, 1, MFLAGS, diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 4ba4007f02a6..a2aa50c8d3ab 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -30,6 +30,7 @@ #define ARMCLKB 9 /* sclk gates (special clocks) */ +#define SCLK_I2SOUT_SRC 64 #define SCLK_I2C1 65 #define SCLK_I2C2 66 #define SCLK_I2C3 67 |