diff options
| author | Wyon Bi <bivvy.bi@rock-chips.com> | 2019-03-11 16:39:28 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2019-03-12 15:53:52 +0800 |
| commit | 26bbb2af075a4c60905c1a8e22e8717f0438658f (patch) | |
| tree | 54da51567bba6d2b62cf1cc6a9713eb4d2de2f91 | |
| parent | bd7ce1902c63ed76b9e3929bf6c21f1b82913ff0 (diff) | |
ARM: dts: rockchip: rk312x-android: set vop-dclk-mode default value to 1
Fix display abnormal caused by DDR frequency conversion.
Change-Id: Iaa3bf6177d42f8ac5f9078b58a138f48d5c1d874
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
| -rw-r--r-- | arch/arm/boot/dts/rk312x-android.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk312x-android.dtsi b/arch/arm/boot/dts/rk312x-android.dtsi index ad76eceaadef..c35c3a05dffc 100644 --- a/arch/arm/boot/dts/rk312x-android.dtsi +++ b/arch/arm/boot/dts/rk312x-android.dtsi @@ -109,6 +109,7 @@ }; &dmc { + vop-dclk-mode = <1>; status = "okay"; }; |