diff options
| author | Rocky Hao <rocky.hao@rock-chips.com> | 2017-03-30 11:46:15 +0800 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2017-04-11 18:30:34 +0800 |
| commit | b913ab69f93fda49fba500188823593f140e724f (patch) | |
| tree | a550705ba34801faeb5618e1e9264ea1635bfb36 | |
| parent | 31e5d7ab03c9f117d198974ded07b20c924e58c9 (diff) | |
arm64: dts: rockchip: add tsadc's working clock rate for rk3288
add tsadc's working clock rate for rk3288. if not set, tsadc
will work at the default rate of 1k hz.
Change-Id: I1b26351c3fb97f5ceb4657c2356c2f5649ad140c
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 1947ef8f9ceb..f7601f4f7bed 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -610,6 +610,8 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <10000>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; |