media: rockchip/isp1: move CSIHOST_PHY_TEST_CTRL0/1 into dphy_drv_data

The offsets are different between RK3288 and RK3399. Move them
into the SoC-specific dphy_drv_data struct.

Without this fix you don't get a stable image on the RK3399.

Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

1 files changed, 21 insertions, 9 deletions

diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
index c0541781725b..90290d0ac774 100644
--- a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
+++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
@@ -86,8 +86,13 @@
 /*
  * CSI HOST
  */
-#define CSIHOST_PHY_TEST_CTRL0		0x30
-#define CSIHOST_PHY_TEST_CTRL1		0x34
+#define RK3288_CSIHOST_PHY_TEST_CTRL0		0x30
+#define RK3288_CSIHOST_PHY_TEST_CTRL1		0x34
+
+/* values acc. to RK3399 TRM and camsys_soc_rk3399.h */
+#define RK3399_CSIHOST_PHY_TEST_CTRL0      0xb4
+#define RK3399_CSIHOST_PHY_TEST_CTRL1      0xb8
+
 #define CSIHOST_PHY_SHUTDOWNZ		0x08
 #define CSIHOST_DPHY_RSTZ		0x0c
 
@@ -251,6 +256,7 @@ struct dphy_drv_data {
 	int num_hsfreq_ranges;
 	const struct dphy_reg *regs;
 	enum mipi_dphy_ctl_type ctl_type;
+	const int phy_test_ctrl[2]; /* CSIHOST_PHY_TEST_CTRL0/1 offsets */
 };
 
 struct sensor_async_subdev {
@@ -325,6 +331,7 @@ static void mipidphy0_wr_reg(struct mipidphy_priv *priv,
 static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr,
 			     unsigned char data)
 {
+	const int *phy_test_ctrl = priv->drv_data->phy_test_ctrl;
 	/*
 	 * TESTEN =1,TESTDIN=addr
 	 * TESTCLK=0
@@ -332,11 +339,11 @@ static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr,
 	 * TESTCLK=1
 	 */
 	writel((PHY_TESTEN_ADDR | addr),
-	       priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL1);
-	writel(0x00, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
+	       priv->txrx_base_addr + phy_test_ctrl[1]);
+	writel(0x00, priv->txrx_base_addr + phy_test_ctrl[0]);
 	writel((PHY_TESTEN_DATA | data),
-	       priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL1);
-	writel(PHY_TESTCLK, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
+	       priv->txrx_base_addr + phy_test_ctrl[1]);
+	writel(PHY_TESTCLK, priv->txrx_base_addr + phy_test_ctrl[0]);
 }
 
 static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq,
@@ -649,6 +656,7 @@ static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv,
 	const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
 	int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
 	int i, hsfreq = 0;
+	const int *phy_test_ctrl = priv->drv_data->phy_test_ctrl;
 
 	for (i = 0; i < num_hsfreq_ranges; i++) {
 		if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
@@ -671,10 +679,11 @@ static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv,
 	/* dphy start */
 	writel(0, priv->txrx_base_addr + CSIHOST_PHY_SHUTDOWNZ);
 	writel(0, priv->txrx_base_addr + CSIHOST_DPHY_RSTZ);
-	writel(PHY_TESTCLK, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
-	writel(PHY_TESTCLR, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
+	writel(PHY_TESTCLK, priv->txrx_base_addr + phy_test_ctrl[0]);
+	writel(PHY_TESTCLR, priv->txrx_base_addr + phy_test_ctrl[0]);
 	usleep_range(100, 150);
-	writel(PHY_TESTCLK, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
+	writel(PHY_TESTCLK, priv->txrx_base_addr + phy_test_ctrl[0]);
+
 	usleep_range(100, 150);
 
 	/* set clock lane */
@@ -756,6 +765,7 @@ static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
 	.num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges),
 	.regs = rk3288_grf_dphy_regs,
 	.ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
+	.phy_test_ctrl = {RK3288_CSIHOST_PHY_TEST_CTRL0, RK3288_CSIHOST_PHY_TEST_CTRL1}
 };
 
 static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
@@ -765,6 +775,7 @@ static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
 	.num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
 	.regs = rk3326_grf_dphy_regs,
 	.ctl_type = MIPI_DPHY_CTL_CSI_HOST,
+	.phy_test_ctrl = {RK3288_CSIHOST_PHY_TEST_CTRL0, RK3288_CSIHOST_PHY_TEST_CTRL1},
 };
 
 static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
@@ -774,6 +785,7 @@ static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
 	.num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges),
 	.regs = rk3399_grf_dphy_regs,
 	.ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
+	.phy_test_ctrl = {RK3399_CSIHOST_PHY_TEST_CTRL0, RK3399_CSIHOST_PHY_TEST_CTRL1}
 };
 
 static const struct of_device_id rockchip_mipidphy_match_id[] = {