diff options
author | Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> | 2018-05-29 18:00:16 +0200 |
---|---|---|
committer | Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> | 2018-05-29 19:25:51 +0200 |
commit | 0b4129dfc353cc17004c6cfea62450b1ddcc0d4a (patch) | |
tree | 02c32f463dcc4f58d5f1d85405c3ef2e1de88111 | |
parent | 5634610d8032cdbac6d7870b6cad3bf96c35c765 (diff) |
media: rockchip/isp1: move GRF_DPHY_RX1_SRC_SEL value into dphy_drv_data
This needs to be set to 0 on the rk3399. With the value set to 1,
we get zero interrupts, with 1, we get 60 (as expected).
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
-rw-r--r-- | drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c index 90290d0ac774..3157b4518ffb 100644 --- a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c +++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c @@ -257,6 +257,7 @@ struct dphy_drv_data { const struct dphy_reg *regs; enum mipi_dphy_ctl_type ctl_type; const int phy_test_ctrl[2]; /* CSIHOST_PHY_TEST_CTRL0/1 offsets */ + const u8 rx1_src_sel; /* value to set GRF_DPHY_RX1_SRC_SEL to */ }; struct sensor_async_subdev { @@ -666,7 +667,7 @@ static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv, } write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1); write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1); - write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1); + write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, drv_data->rx1_src_sel); write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0); write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1); /* Disable lan turn around, which is ignored in receive mode */ @@ -765,7 +766,8 @@ static const struct dphy_drv_data rk3288_mipidphy_drv_data = { .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges), .regs = rk3288_grf_dphy_regs, .ctl_type = MIPI_DPHY_CTL_GRF_ONLY, - .phy_test_ctrl = {RK3288_CSIHOST_PHY_TEST_CTRL0, RK3288_CSIHOST_PHY_TEST_CTRL1} + .phy_test_ctrl = {RK3288_CSIHOST_PHY_TEST_CTRL0, RK3288_CSIHOST_PHY_TEST_CTRL1}, + .rx1_src_sel = 1, }; static const struct dphy_drv_data rk3326_mipidphy_drv_data = { @@ -776,6 +778,7 @@ static const struct dphy_drv_data rk3326_mipidphy_drv_data = { .regs = rk3326_grf_dphy_regs, .ctl_type = MIPI_DPHY_CTL_CSI_HOST, .phy_test_ctrl = {RK3288_CSIHOST_PHY_TEST_CTRL0, RK3288_CSIHOST_PHY_TEST_CTRL1}, + .rx1_src_sel = 1, }; static const struct dphy_drv_data rk3399_mipidphy_drv_data = { @@ -785,7 +788,8 @@ static const struct dphy_drv_data rk3399_mipidphy_drv_data = { .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges), .regs = rk3399_grf_dphy_regs, .ctl_type = MIPI_DPHY_CTL_GRF_ONLY, - .phy_test_ctrl = {RK3399_CSIHOST_PHY_TEST_CTRL0, RK3399_CSIHOST_PHY_TEST_CTRL1} + .phy_test_ctrl = {RK3399_CSIHOST_PHY_TEST_CTRL0, RK3399_CSIHOST_PHY_TEST_CTRL1}, + .rx1_src_sel = 0, }; static const struct of_device_id rockchip_mipidphy_match_id[] = { |