diff options
| author | Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> | 2018-05-24 12:34:47 +0200 |
|---|---|---|
| committer | Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> | 2018-05-24 12:34:47 +0200 |
| commit | ed7939c68aa330595fe96701be0689cd6bf9127c (patch) | |
| tree | 465e369c11db21a48e7387a59470c23e4d001958 | |
| parent | 70514eee0b370816b7a7c1dc6946dd75624eebd8 (diff) | |
[IN PROGRESS] rockchip isp1: tx1rx1 fixes for RK3399
For the RK3399, tx1rx1 support is incomplete in the driver.
| -rw-r--r-- | drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c | 36 |
1 files changed, 31 insertions, 5 deletions
diff --git a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c index 72b1876cdd03..32a7535e8131 100644 --- a/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c +++ b/drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c @@ -636,6 +636,10 @@ static int mipidphy_rx_stream_on(struct mipidphy_priv *priv, return 0; } +// Compare with camsys_soc_rk3399.c / camsys_rk3399_mipihpy_cfg() + +#define BEHAVE_LIKE_MARVIN 1 + static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv, struct v4l2_subdev *sd) { @@ -652,25 +656,40 @@ static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv, break; } } - write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1); - write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1); + // write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1); // not defined for RK3399 + // write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1); // not defined for RK3399 + +#if BEHAVE_LIKE_MARVIN + write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 0); // PHY_REG(RK3399_GRF_SOC_CON24, 1, 4) +#else write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1); - write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0); - write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1); +#endif + + write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0); // PHY_REG(RK3399_GRF_SOC_CON24, 1, 7) + write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1); // PHY_REG(RK3399_GRF_SOC_CON24, 1, 5) /* Disable lan turn around, which is ignored in receive mode */ write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0); write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0); - write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0); + write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0); // GRF_SOC_CON24 offset 0 width 4 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf); write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE, GENMASK(sensor->lanes - 1, 0)); /* dphy start */ writel(0, priv->txrx_base_addr + CSIHOST_PHY_SHUTDOWNZ); writel(0, priv->txrx_base_addr + CSIHOST_DPHY_RSTZ); +#if BEHAVE_LIKE_MARVIN +#define CAMSYS_DSIHOST_PHY_TEST_CTRL0 (0x00b4) + writel(PHY_TESTCLK, priv->txrx_base_addr + CAMSYS_DSIHOST_PHY_TEST_CTRL0); + writel(PHY_TESTCLR, priv->txrx_base_addr + CAMSYS_DSIHOST_PHY_TEST_CTRL0); + usleep_range(100, 150); + writel(PHY_TESTCLK, priv->txrx_base_addr + CAMSYS_DSIHOST_PHY_TEST_CTRL0); +#else writel(PHY_TESTCLK, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0); writel(PHY_TESTCLR, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0); usleep_range(100, 150); writel(PHY_TESTCLK, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0); +#endif + usleep_range(100, 150); /* set clock lane */ @@ -683,6 +702,13 @@ static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv, mipidphy1_wr_reg(priv, HS_RX_DATA_LANES_THS_SETTLE_CONTROL, THS_SETTLE_COUNTER_THRESHOLD); +#if BEHAVE_LIKE_MARVIN +#define CAMSYS_DSIHOST_PHY_TEST_CTRL1 (0x00b8) + mipidphy1_wr_reg(priv, CAMSYS_DSIHOST_PHY_TEST_CTRL0, 0x00000002); + mipidphy1_wr_reg(priv, CAMSYS_DSIHOST_PHY_TEST_CTRL1, 0x00000000); + mipidphy1_wr_reg(priv, CSIHOST_DPHY_RSTZ, 0x00000002); +#endif + /* Normal operation */ mipidphy1_wr_reg(priv, 0x0, 0); |