diff options
| author | Greg Hackmann <ghackmann@google.com> | 2017-10-04 09:31:34 -0700 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-01-11 10:44:28 +0800 |
| commit | fe1b88d895b85dafde1a740fcfb4253a6b11a48a (patch) | |
| tree | b08beb9b611616cd1464ecdf8dd3c56b1366775d | |
| parent | e35b7d275946868629fd8fa1df2c7d07abb5c8a5 (diff) | |
arm64: issue isb when trapping CNTVCT_EL0 access
CVE-2017-13218
Change-Id: I6005a6e944494257bfc2243fde2f7a09c3fd76c6
| -rw-r--r-- | arch/arm64/kernel/traps.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 1b80da8d986e..cc229e5b6c04 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -33,6 +33,7 @@ #include <linux/syscalls.h> #include <asm/atomic.h> +#include <asm/barrier.h> #include <asm/bug.h> #include <asm/debug-monitors.h> #include <asm/esr.h> @@ -413,6 +414,7 @@ static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) { int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; + isb(); if (rt != 31) regs->regs[rt] = arch_counter_get_cntvct(); regs->pc += 4; |