diff options
| author | Wyon Bi <bivvy.bi@rock-chips.com> | 2018-01-05 10:09:35 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-01-11 16:48:20 +0800 |
| commit | 886d0dc5826acb3881fcd2dfa2e43743dca06a58 (patch) | |
| tree | 3b82be49b20e66409ddc428235dd1ad23789c6c2 | |
| parent | dffc88904250b7bffc0c3b5a7b3a667f55baa992 (diff) | |
arm64: dts: rockchip: Add mipi_dphy node for PX30
Change-Id: I92c6bfe60dfe0c89befddad528c8d41a2318567a
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 6a6447bf9e2e..a021570c7400 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -558,6 +558,21 @@ <75000000>, <416000000>; }; + mipi_dphy: mipi-dphy@ff2e0000 { + compatible = "rockchip,px30-mipi-dphy"; + reg = <0x0 0xff2e0000 0x0 0x10000>; + clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; + clock-names = "ref", "pclk"; + clock-output-names = "mipi_dphy_pll"; + #clock-cells = <0>; + resets = <&cru SRST_MIPIDSIPHY_P>; + reset-names = "apb"; + power-domains = <&power PX30_PD_VO>; + #phy-cells = <0>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + lvds: lvds@ff2e0000 { compatible = "rockchip,px30-lvds"; reg = <0x0 0xff2e0000 0x0 0x100>, <0x0 0xff2e0100 0x0 0x100>; |