From 2f78eae5064728d6cd907148cfeaf8ba3e63b0ef Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 23 Jun 2014 15:15:54 -0700 Subject: ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun Signed-off-by: Varun Sethi Signed-off-by: Arnab Basu --- include/common.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include/common.h') diff --git a/include/common.h b/include/common.h index cc74633df5..2e5a6d3d2f 100644 --- a/include/common.h +++ b/include/common.h @@ -687,9 +687,6 @@ ulong get_PERCLK3(void); ulong get_bus_freq (ulong); int get_serial_clock(void); -#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) -ulong get_ddr_freq(ulong); -#endif #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); @@ -705,6 +702,8 @@ static inline ulong get_ddr_freq(ulong dummy) { return get_bus_freq(dummy); } +#else +ulong get_ddr_freq(ulong); #endif #if defined(CONFIG_4xx) -- cgit v1.2.3