From a80a65e99745c3c2138716d2a1c58096e8e71697 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 6 Apr 2015 11:23:07 -0300 Subject: mx53loco: Disable printing cpuinfo Since commit 32df39c741788e ("mx5: fix get_reset_cause") we have the following boot messages on a mx53qsb: U-Boot 2015.04-rc5-00029-gd68df02 (Apr 06 2015 - 11:15:39) CPU: Freescale i.MX53 rev2.1 at 800 MHz Reset cause: POR Board: MX53 LOCO I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial CPU: Freescale i.MX53 rev2.1 at 1000 MHz Reset cause: unknown reset Net: FEC [PRIME] The CPU and Reset cause lines appear twice. Initially mx53 boots at 800MHz, then at a later point the PMIC is configured via I2C to raise the CPU voltage so that it can run at 1GHz. To avoid such misleading double printings, disable printing cpu info for now. Signed-off-by: Fabio Estevam Acked-by: Jason Liu --- board/freescale/mx53loco/mx53loco.c | 1 - include/configs/mx53loco.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 9ece6ecd8b..1298788624 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -389,7 +389,6 @@ int board_late_init(void) { if (!power_init()) clock_1GHz(); - print_cpuinfo(); return 0; } diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 8f92234471..3551e02276 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_DISPLAY_CPUINFO - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -- cgit v1.2.3 From f97d112eb6c18e6947e054ee6b39afea724a7e9a Mon Sep 17 00:00:00 2001 From: Ulises Cardenas Date: Fri, 27 Mar 2015 08:08:57 -0600 Subject: Fix mxc_hab documenation for DEK blob generation Include/fsl_sec.h defines sec_in and sec_out, according to the platform's endianess. Therefore, CONFIG_SYS_FSL_LE needs to be declared in the configuration file of the target, in order to use enable the DEK blob generation command. This requirement is not explicit in the README.mxc_hab. Signed-off-by: Ulises Cardenas --- doc/README.mxc_hab | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab index e9340dd14c..a1b1d348ed 100644 --- a/doc/README.mxc_hab +++ b/doc/README.mxc_hab @@ -69,6 +69,7 @@ CONFIG_SECURE_BOOT CONFIG_SYS_FSL_SEC_COMPAT 4 /* HAB version */ CONFIG_FSL_CAAM CONFIG_CMD_DEKBLOB +CONFIG_SYS_FSL_LE Note: The encrypted boot feature is only supported by HABv4 or greater. -- cgit v1.2.3 From 424ee3d1571ebea9d6373c7c8cf408ffa655ff52 Mon Sep 17 00:00:00 2001 From: Andrej Rosano Date: Wed, 8 Apr 2015 18:56:29 +0200 Subject: ARM: mx5: move to a standard arch/board approach Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the commit: 89ebc82137bebb11a8191f8b9cbf08f2533ae8bc Signed-off-by: Andrej Rosano Cc: Stefano Babic Cc: Vagrant Cascadian Tested-by: Chris Kuethe --- arch/arm/Kconfig | 6 ++++++ arch/arm/cpu/armv7/mx5/Kconfig | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx5/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c0a0fd842a..06b8e58a32 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -437,6 +437,10 @@ config ARCH_MX6 bool "Freescale MX6" select CPU_V7 +config ARCH_MX5 + bool "Freescale MX5" + select CPU_V7 + config TARGET_M53EVK bool "Support m53evk" select CPU_V7 @@ -741,6 +745,8 @@ source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/cpu/armv7/mx6/Kconfig" +source "arch/arm/cpu/armv7/mx5/Kconfig" + source "arch/arm/mach-nomadik/Kconfig" source "arch/arm/cpu/armv7/omap3/Kconfig" diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig new file mode 100644 index 0000000000..960a718d41 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/Kconfig @@ -0,0 +1,16 @@ +if ARCH_MX5 + +config MX5 + bool + default y + +config MX51 + bool + +config MX53 + bool + +config SYS_SOC + default "mx5" + +endif -- cgit v1.2.3 From 3bf801a2176e3330a3ef696d974d0d198d99b7e9 Mon Sep 17 00:00:00 2001 From: Andrej Rosano Date: Wed, 8 Apr 2015 18:56:30 +0200 Subject: ARM: mx5: add support for USB armory board Add support for Inverse Path USB armory board, an open source flash-drive sized computer based on Freescale i.MX53 SoC. http://inversepath.com/usbarmory Signed-off-by: Andrej Rosano Cc: Stefano Babic Cc: Chris Kuethe Cc: Fabio Estevam Cc: Vagrant Cascadian Tested-By: Vagrant Cascadian Tested-by: Chris Kuethe --- arch/arm/cpu/armv7/mx5/Kconfig | 11 + board/inversepath/usbarmory/Kconfig | 15 ++ board/inversepath/usbarmory/MAINTAINERS | 6 + board/inversepath/usbarmory/Makefile | 10 + board/inversepath/usbarmory/imximage.cfg | 82 ++++++ board/inversepath/usbarmory/usbarmory.c | 417 +++++++++++++++++++++++++++++++ configs/usbarmory_defconfig | 3 + include/configs/usbarmory.h | 126 ++++++++++ 8 files changed, 670 insertions(+) create mode 100644 board/inversepath/usbarmory/Kconfig create mode 100644 board/inversepath/usbarmory/MAINTAINERS create mode 100644 board/inversepath/usbarmory/Makefile create mode 100644 board/inversepath/usbarmory/imximage.cfg create mode 100644 board/inversepath/usbarmory/usbarmory.c create mode 100644 configs/usbarmory_defconfig create mode 100644 include/configs/usbarmory.h diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig index 960a718d41..2d6c0ce29d 100644 --- a/arch/arm/cpu/armv7/mx5/Kconfig +++ b/arch/arm/cpu/armv7/mx5/Kconfig @@ -10,7 +10,18 @@ config MX51 config MX53 bool +choice + prompt "MX5 board select" + +config TARGET_USBARMORY + bool "Support USB armory" + select CPU_V7 + +endchoice + config SYS_SOC default "mx5" +source "board/inversepath/usbarmory/Kconfig" + endif diff --git a/board/inversepath/usbarmory/Kconfig b/board/inversepath/usbarmory/Kconfig new file mode 100644 index 0000000000..c2cd54437d --- /dev/null +++ b/board/inversepath/usbarmory/Kconfig @@ -0,0 +1,15 @@ +if TARGET_USBARMORY + +config IMX_CONFIG + default "board/inversepath/usbarmory/imximage.cfg" + +config SYS_BOARD + default "usbarmory" + +config SYS_VENDOR + default "inversepath" + +config SYS_CONFIG_NAME + default "usbarmory" + +endif diff --git a/board/inversepath/usbarmory/MAINTAINERS b/board/inversepath/usbarmory/MAINTAINERS new file mode 100644 index 0000000000..71a3dd40f1 --- /dev/null +++ b/board/inversepath/usbarmory/MAINTAINERS @@ -0,0 +1,6 @@ +USBARMORY BOARD +M: Andrej Rosano +S: Maintained +F: board/inversepath/usbarmory/ +F: include/configs/usbarmory.h +F: configs/usbarmory_defconfig diff --git a/board/inversepath/usbarmory/Makefile b/board/inversepath/usbarmory/Makefile new file mode 100644 index 0000000000..9b8bd80ab3 --- /dev/null +++ b/board/inversepath/usbarmory/Makefile @@ -0,0 +1,10 @@ +# +# USB armory MkI board Makefile +# http://inversepath.com/usbarmory +# +# Copyright (C) 2015, Inverse Path +# Andrej Rosano +# +# SPDX-License-Identifier:|____GPL-2.0+ + +obj-y := usbarmory.o diff --git a/board/inversepath/usbarmory/imximage.cfg b/board/inversepath/usbarmory/imximage.cfg new file mode 100644 index 0000000000..392d2f91ed --- /dev/null +++ b/board/inversepath/usbarmory/imximage.cfg @@ -0,0 +1,82 @@ +/* + * USB armory MkI board imximage configuration + * http://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano + * + * SPDX-License-Identifier:|____GPL-2.0+ + */ + +IMAGE_VERSION 2 +BOOT_FROM sd + + +/* IOMUX */ + +DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ +DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ +DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ +DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ + +DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ +DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ +DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ + +DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ +DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ +DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ + +DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ +DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ +DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ + +DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ +DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ +DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ + +DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK0 */ +DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK1 */ + +DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ +DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ +DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDS */ +DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ + +DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ +DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ + + +/* ESDCTL */ + +DATA 4 0x63fd9000 0x84180000 /* ESDCTL_ESDCTL */ + +DATA 4 0x63fd9004 0x0002002d /* ESDCTL_ESDPTC */ +DATA 4 0x63fd9008 0x12273030 /* ESDCTL_ESDOTC */ +DATA 4 0x63fd900c 0x9f5152e3 /* ESDCTL_ESDCFG0 */ +DATA 4 0x63fd9010 0xb68e8a63 /* ESDCTL_ESDCFG1 */ +DATA 4 0x63fd9014 0x01ff00db /* ESDCTL_ESDCFG2 */ +DATA 4 0x63fd9018 0x00011740 /* ESDCTL_ESDMISC */ + +DATA 4 0x63fd901c 0x00008032 /* ESDCTL_ESDSCR */ +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x05208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd901c 0x00000000 + +DATA 4 0x63fd9020 0x00005800 /* ESDCTL_ESDREF */ +DATA 4 0x63fd902c 0x000026d2 /* ESDCTL_ESDEWD */ +DATA 4 0x63fd9030 0x009f0e21 /* ESDCTL_ESDOR */ +DATA 4 0x63fd9040 0x05380003 /* ESDCTL_ZQHWCTRL */ +DATA 4 0x63fd9058 0x00022227 /* ESDCTL_ODTCTRL */ + +DATA 4 0x63fd907c 0x01370138 /* ESDCTL_DGCTRL0 */ +DATA 4 0x63fd9080 0x013b013c /* ESDCTL_DGCTRL1 */ +DATA 4 0x63fd9088 0x35343535 /* ESDCTL_RDDLCTL */ +DATA 4 0x63fd9090 0x4d444c44 /* ESDCTL_WRDLCTL */ diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c new file mode 100644 index 0000000000..a809039ac5 --- /dev/null +++ b/board/inversepath/usbarmory/usbarmory.c @@ -0,0 +1,417 @@ +/* + * USB armory MkI board initialization + * http://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {MMC_SDHC1_BASE_ADDR} +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* CD not present */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + return ret; +} + +#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP) +#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) +#define PAD_CTRL_UP PAD_CTL_PUS_100K_UP +#define PAD_CTRL_GND PAD_CTL_PUS_100K_DOWN + +static void setup_iomux_sd(void) +{ + static const iomux_v3_cfg_t pads[] = { + NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_SDHC_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, + MX53_SDHC_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, + MX53_SDHC_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, + MX53_SDHC_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + MX53_SDHC_PAD_CTRL), + MX53_PAD_EIM_DA13__GPIO3_13, + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_led(void) +{ + static const iomux_v3_cfg_t pads[] = { + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT6__GPIO4_27, + PAD_CTL_PUS_100K_DOWN), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t pads[] = { + NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_pinheader(void) +{ + static const iomux_v3_cfg_t pads[] = { + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__GPIO5_26, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__GPIO5_27, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, + MX53_UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, + MX53_UART_PAD_CTRL), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__GPIO5_30, PAD_CTRL_UP), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_unused_boot(void) +{ + static const iomux_v3_cfg_t pads[] = { + /* Pulled-up pads */ + NEW_PAD_CTRL(MX53_PAD_EIM_A21__GPIO2_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA0__GPIO3_0, PAD_CTRL_UP), + + /* Grounded pads */ + NEW_PAD_CTRL(MX53_PAD_EIM_LBA__GPIO2_27, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_EB0__GPIO2_28, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_EB1__GPIO2_29, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A18__GPIO2_20, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A19__GPIO2_19, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A20__GPIO2_18, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_A22__GPIO2_16, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA1__GPIO3_1, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA2__GPIO3_2, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA3__GPIO3_3, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA4__GPIO3_4, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA5__GPIO3_5, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA6__GPIO3_6, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA7__GPIO3_7, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA8__GPIO3_8, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA9__GPIO3_9, PAD_CTRL_GND), + NEW_PAD_CTRL(MX53_PAD_EIM_DA10__GPIO3_10, PAD_CTRL_GND), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +static void setup_iomux_unused_nc(void) +{ + /* Out of reset values define the pin values before the + ROM is executed so we force all the not connected pins + to a known state */ + static const iomux_v3_cfg_t pads[] = { + /* CONTROL PINS block */ + NEW_PAD_CTRL(MX53_PAD_GPIO_0__GPIO1_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_3__GPIO1_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_5__GPIO1_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_6__GPIO1_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_7__GPIO1_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_8__GPIO1_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_9__GPIO1_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_11__GPIO4_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_12__GPIO4_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_13__GPIO4_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_14__GPIO4_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_16__GPIO7_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_17__GPIO7_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_18__GPIO7_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_GPIO_19__GPIO4_5, PAD_CTRL_UP), + + /* EIM block */ + NEW_PAD_CTRL(MX53_PAD_EIM_OE__GPIO2_25, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_WAIT__GPIO5_0, PAD_CTRL_UP), + /* EIM_LBA: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_RW__GPIO2_26, PAD_CTRL_UP), + /* EIM_EB0: setup_iomux_unused_boot() */ + /* EIM_EB1: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_EB2__GPIO2_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_CS0__GPIO2_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_CS1__GPIO2_24, PAD_CTRL_UP), + /* EIM_A16: setup_iomux_unused_boot() */ + /* EIM_A17: setup_iomux_unused_boot() */ + /* EIM_A18: setup_iomux_unused_boot() */ + /* EIM_A19: setup_iomux_unused_boot() */ + /* EIM_A20: setup_iomux_unused_boot() */ + /* EIM_A21: setup_iomux_unused_boot() */ + /* EIM_A22: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_A23__GPIO6_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_A24__GPIO5_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_A25__GPIO5_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D16__GPIO3_16, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D17__GPIO3_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D18__GPIO3_18, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D19__GPIO3_19, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D20__GPIO3_20, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D21__GPIO3_21, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D22__GPIO3_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D23__GPIO3_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D27__GPIO3_27, PAD_CTRL_UP), + /* EIM_D28: setup_iomux_unused_boot() */ + /* EIM_D29: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, PAD_CTRL_UP), + /* EIM_DA0: setup_iomux_unused_boot() */ + /* EIM_DA1: setup_iomux_unused_boot() */ + /* EIM_DA2: setup_iomux_unused_boot() */ + /* EIM_DA3: setup_iomux_unused_boot() */ + /* EIM_DA4: setup_iomux_unused_boot() */ + /* EIM_DA5: setup_iomux_unused_boot() */ + /* EIM_DA6: setup_iomux_unused_boot() */ + /* EIM_DA7: setup_iomux_unused_boot() */ + /* EIM_DA8: setup_iomux_unused_boot() */ + /* EIM_DA9: setup_iomux_unused_boot() */ + /* EIM_DA10: setup_iomux_unused_boot() */ + NEW_PAD_CTRL(MX53_PAD_EIM_DA11__GPIO3_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA12__GPIO3_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA13__GPIO3_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA14__GPIO3_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_EIM_DA15__GPIO3_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__GPIO6_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__GPIO6_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__GPIO6_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__GPIO6_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__GPIO6_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__GPIO6_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__GPIO6_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__GPIO6_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_NANDF_CS3__GPIO6_16, PAD_CTRL_UP), + + /* MISC block */ + NEW_PAD_CTRL(MX53_PAD_FEC_MDC__GPIO1_31, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__GPIO1_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__GPIO1_25, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__GPIO1_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__GPIO1_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__GPIO1_28, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__GPIO1_27, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__GPIO1_26, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__GPIO1_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__GPIO1_29, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL0__GPIO4_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__GPIO4_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL1__GPIO4_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__GPIO4_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL2__GPIO4_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__GPIO4_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL3__GPIO4_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__GPIO4_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_COL4__GPIO4_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_KEY_ROW4__GPIO4_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_CMD__GPIO1_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_CLK__GPIO1_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__GPIO1_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__GPIO1_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__GPIO1_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__GPIO1_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_BUFFER_EN__GPIO7_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_CS_0__GPIO7_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_CS_1__GPIO7_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DA_0__GPIO7_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DA_1__GPIO7_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DA_2__GPIO7_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__GPIO2_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__GPIO2_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__GPIO2_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__GPIO2_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__GPIO2_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__GPIO2_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__GPIO2_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__GPIO2_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__GPIO2_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__GPIO2_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__GPIO2_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__GPIO2_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__GPIO2_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__GPIO2_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__GPIO2_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__GPIO2_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DIOR__GPIO7_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__GPIO6_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__GPIO6_18, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_DMARQ__GPIO7_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_INTRQ__GPIO7_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__GPIO7_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__GPIO7_4, PAD_CTRL_UP), + + /* IPU block */ + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT4__GPIO5_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT5__GPIO5_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT6__GPIO5_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT7__GPIO5_25, PAD_CTRL_UP), + /* CSI0_DAT8: setup_iomux_pinheader() */ + /* CSI0_DAT9: setup_iomux_pinheader() */ + /* CSI0_DAT10: setup_iomux_pinheader() */ + /* CSI0_DAT11: setup_iomux_pinheader() */ + /* CSI0_DAT12: setup_iomux_pinheader() */ + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__GPIO5_31, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT14__GPIO6_0, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT15__GPIO6_1, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT16__GPIO6_2, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT17__GPIO6_3, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT18__GPIO6_4, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DAT19__GPIO6_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_VSYNC__GPIO5_21, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_PIXCLK__GPIO5_18, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_MCLK__GPIO5_19, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_CSI0_DATA_EN__GPIO5_20, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_PIN2__GPIO4_18, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_PIN3__GPIO4_19, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_PIN15__GPIO4_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT0__GPIO4_21, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT1__GPIO4_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT2__GPIO4_23, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT3__GPIO4_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT4__GPIO4_25, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT5__GPIO4_26, PAD_CTRL_UP), + /* DISP0_DAT6: setup_iomux_led() */ + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT7__GPIO4_28, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT8__GPIO4_29, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT9__GPIO4_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT10__GPIO4_31, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT11__GPIO5_5, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT12__GPIO5_6, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT13__GPIO5_7, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT14__GPIO5_8, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT15__GPIO5_9, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT16__GPIO5_10, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT17__GPIO5_11, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT18__GPIO5_12, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT19__GPIO5_13, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT20__GPIO5_14, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT21__GPIO5_15, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT22__GPIO5_16, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DISP0_DAT23__GPIO5_17, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_DI0_DISP_CLK__GPIO4_16, PAD_CTRL_UP), + + /* LVDS block */ + NEW_PAD_CTRL(MX53_PAD_LVDS0_TX0_P__GPIO7_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS0_TX1_P__GPIO7_28, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS0_TX2_P__GPIO7_26, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS0_TX3_P__GPIO7_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_TX0_P__GPIO6_30, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_TX1_P__GPIO6_28, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_TX2_P__GPIO6_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_TX3_P__GPIO6_22, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS0_CLK_P__GPIO7_24, PAD_CTRL_UP), + NEW_PAD_CTRL(MX53_PAD_LVDS1_CLK_P__GPIO6_26, PAD_CTRL_UP), + }; + + imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)); +} + +#define CPU_CLOCK 800 + +static void set_clock(void) +{ + u32 ref_clk = MXC_HCLK; + const uint32_t cpuclk = CPU_CLOCK; + const uint32_t dramclk = 400; + int ret; + + ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to %dMHZ failed\n", cpuclk); + + ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); + if (ret) + printf("CPU: Switch peripheral clock to %dMHz failed\n", + dramclk); + + ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); +} + +int board_early_init_f(void) +{ + setup_iomux_unused_nc(); + setup_iomux_unused_boot(); + setup_iomux_sd(); + setup_iomux_led(); + setup_iomux_pinheader(); + set_clock(); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + setup_iomux_i2c(); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30); + return 0; +} + +int checkboard(void) +{ + puts("Board: Inverse Path USB armory MkI\n"); + return 0; +} diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig new file mode 100644 index 0000000000..10bdd9ec40 --- /dev/null +++ b/configs/usbarmory_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX5=y +CONFIG_TARGET_USBARMORY=y diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h new file mode 100644 index 0000000000..f29ab2d2d7 --- /dev/null +++ b/include/configs/usbarmory.h @@ -0,0 +1,126 @@ +/* + * USB armory MkI board configuration settings + * http://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano + * + * SPDX-License-Identifier:|____GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX53 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_MXC_GPIO + +#include +#include + +#include + +/* U-Boot commands */ +#define CONFIG_CMD_MEMTEST +#undef CONFIG_CMD_IMLS + +/* U-Boot environment */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* U-Boot general configurations */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* UART */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* SD/MMC */ +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_STORAGE +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC + +/* Fuse */ +#define CONFIG_CMD_FUSE +#define CONFIG_FSL_IIM + +/* Linux boot */ +#define CONFIG_LOADADDR 0x72000000 +#define CONFIG_SYS_TEXT_BASE 0x77800000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_HOSTNAME usbarmory +#define CONFIG_BOOTCOMMAND \ + "run distro_bootcmd; " \ + "setenv bootargs console=${console} ${bootargs_default}; " \ + "ext2load mmc 0:1 ${kernel_addr_r} /boot/uImage; " \ + "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}" + +#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) + +#include + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r=0x70800000\0" \ + "fdt_addr_r=0x71000000\0" \ + "scriptaddr=0x70800000\0" \ + "pxefile_addr_r=0x70800000\0" \ + "ramdisk_addr_r=0x73000000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \ + "fdtfile=imx53-usbarmory.dtb\0" \ + "console=ttymxc0,115200\0" \ + BOOTENV + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM CSD0_BASE_ADDR +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x90000000 + +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#endif /* __CONFIG_H */ -- cgit v1.2.3