Age | Commit message (Collapse) | Author |
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a wrong shift in the emmc cid resulted in duplicated
mac addresses. use the correct emmc product serialnumber bits instead
of the manufacturing date
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Toshiba eMMC requires a longer delay to work proper with spl
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command that returns true if the first mmc device is the on-board emmc.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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We have seen axp221 with all zeros in the sid registers.
Therefore we base our mac address and serial number on the eMMC
serial number as this is the only unique id on the board.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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Including "u-boot" in the prompt makes it clear to the user that
he is in the u-boot shell and not in Linux.
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Also add compatability symlink
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Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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board specific settings should only be done if the specific board is
selected via Kconfig. so we put ifdefs around the relevant sections
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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USBH3 is used as full speed USB connection to the onboard
STM32.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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Signed-off-by: Octav Zlatior <octav.zlatior@theobroma-systems.com>
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The driver currently only supports sun6i.
Signed-off-by: Octav Zlatior <octav.zlatior@theobroma-systems.com>
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Signed-off-by: Octav Zlatior <octav.zlatior@theobroma-systems.com>
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* enabled them for pangolin dts
Signed-off-by: Octav Zlatior <octav.zlatior@theobroma-systems.com>
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The driver model display driver is based on sunxi_display.c
It is currently backwards compatible with the console driver (which
is not driver-model, see TODOs)
Devices can be defined via the dts
Note that using of reg base addresses from dts is only partly implemented,
since some functions in the old sunxi_display are used by both hdmi and
lvds modes; these would need to be separated (or both addresses have to
be specified in the device tree) (see TODOs)
Currently supported modes:
* lvds: single-channel
* hdmi (with EDID)
Currently unsupported modes:
* parallel lcd
* vga
Signed-off-by: Octav Zlatior <octav.zlatior@theobroma-systems.com>
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selecting the mmc boot device based on mmc content can fail if the
device is booted from eMMC and there is a SD-card with u-boot plugged
in.
On sun6i we can ѕelect the correct boot device based on the hardware
configuration pins in BOOT_SEL. We only want to do this if UBOOT_SEL is
not active since this overrides the BOOT_SEL settings to SD card.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
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when powered by ATX the SUS3 line must be HIGH to enable the ATX
power supply.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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Increase the DRAM clk from 312 to 360MHz on A31 Pangolin board.
Tests have shown that this clock speed is stable.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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switch to ACIN even if it's shorted with VBUS
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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replaces the generic penguin logo with a vendor specific.
if there is no sunxi.bmp available it will fall back to denx.bmp
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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the current makefile infrastructure only allows BOARD and VENDOR
specific logos, so we have to use sunxi.bmp as logo name if we don't
want to duplicate all the sunxi code.
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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we need to do board specific things that we can't select only based on
the CPU flavor. So we introduce the Kconfig option to select a specfic
sunxi board
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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previous commits fixed on board ethernet. so no need for usb ethernet
anymore
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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removed leftover from hummingbird dts
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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should be done via devicetree
but this require to enhance the micrel driver quite a bit
so let's do this hack instead which breaks every other sun6i device
other then pangolin
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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The P2WI controller acknowledges a soft-reset by auto-clearing the
reset-bit. Instead of waiting for a "magic" number of cycles, we
now wait until the reset-bit deasserts.
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added pin definitions for i2c3_pins_a and mmc2_pins_a
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defconfig for the A31 based uQseven board pangolin from Theobroma
Systems
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PLL5-DDR is different from other PLLs by having an additional
auto-clearing UPD bit (that validates the PLL and needs to be set
after any change to the PLL5 configuration).
The manual requires the following steps to set up PLL5:
1. Set up operational parameters.
2. Enabled the PLL (PLL5_ENABLE bit).
3. Set the UPD-bit (variously referred to as bit 20 or SDRPLL_UPD
in the manual) and wait for it to clear.
4. Wait for the LOCK bit to assert.
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The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
their meaning reversed. This is fixed by this change-set. With this
changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
as setting the voltage to 1.37v (which it had done all along, even
though stating a different target voltage).
After changing the PLL LDO setting, it will take a little while for
the voltage output to settle. A sdelay()-based loop waits the same
order of magnitude as Boot1.
Furthermore, a bit of documentation is added to clarify that the
required setting for the PLL LDO is 1.37v as per the A31 manual.
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This replaces the previous initialization of PLL6 using a magic
value instead of a properly constructed setting for 600MHz and
documents the recommendation/requirement to have PLL6 operating
at 600MHz.
The following issues with the original intialization sequence are
fixed with this:
* we now wait for PLL6 to lock, before proceeding
* we no longer write the lock-bit (which is specified R/O)
* we don't write the (unused) bits where other PLLs have their
divider configuration field
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This change syncs up the multipliers and dividers used to initialize
PLL1 (i.e. the fast clock driving the ARM cores) with the values used
in Allwinner's Boot1 on sun6i.
More specifically, the following settings are now used:
* up to 768MHz: mul=2, div=2 (was: mul=1, div=1)
* up to 1152MHz: mul=3, div=2 (unchanged)
* above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
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This unifies the handling of PLL updates for sun6i (A31) by waiting
for the PLL lock bit of an updated PLL. This changes the previous
practice of either waiting for a "magic" duration using sdelay()
or not waiting at all.
Note, that we can't use a timer-based timeout, as the PLL update
may affect the timekeeping.
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Signed-off-by: Tom Rini <trini@konsulko.com>
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