diff options
Diffstat (limited to 'arch')
116 files changed, 1479 insertions, 2247 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 3d419bca3e..ca617e75ab 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1,3 +1,10 @@ +config HAVE_GENERIC_BOARD + bool + +config SYS_GENERIC_BOARD + bool + depends on HAVE_GENERIC_BOARD + choice prompt "Architecture select" default SANDBOX @@ -5,34 +12,48 @@ choice config ARC bool "ARC architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config ARM bool "ARM architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD select SUPPORT_OF_CONTROL config AVR32 bool "AVR32 architecture" + select HAVE_GENERIC_BOARD config BLACKFIN bool "Blackfin architecture" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config M68K bool "M68000 architecture" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config MICROBLAZE bool "MicroBlaze architecture" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config MIPS bool "MIPS architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config NDS32 bool "NDS32 architecture" config NIOS2 bool "Nios II architecture" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD config OPENRISC bool "OpenRISC architecture" @@ -40,10 +61,13 @@ config OPENRISC config PPC bool "PowerPC architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD select SUPPORT_OF_CONTROL config SANDBOX bool "Sandbox" + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL config SH @@ -56,6 +80,8 @@ config SPARC config X86 bool "x86 architecture" select HAVE_PRIVATE_LIBGCC + select HAVE_GENERIC_BOARD + select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL endchoice diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 4fcd4076c4..04c034b637 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -57,6 +57,3 @@ LDFLAGS_FINAL += -pie # Load address for standalone apps CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 - -# Support generic board on ARC -__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h index b4e9099fb1..8936f5cdf7 100644 --- a/arch/arc/include/asm/config.h +++ b/arch/arc/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef __ASM_ARC_CONFIG_H_ #define __ASM_ARC_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_ARCH_EARLY_INIT_R diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c0a0fd842a..80b0d34190 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -286,13 +286,8 @@ config TARGET_MX35PDK bool "Support mx35pdk" select CPU_ARM1136 -config TARGET_RPI - bool "Support rpi" - select CPU_ARM1176 - -config TARGET_RPI_2 - bool "Support rpi_2" - select CPU_V7 +config ARCH_BCM283X + bool "Broadcom BCM283X family" config TARGET_INTEGRATORAP_CM946ES bool "Support integratorap_cm946es" @@ -727,9 +722,9 @@ endchoice source "arch/arm/mach-at91/Kconfig" -source "arch/arm/mach-davinci/Kconfig" +source "arch/arm/mach-bcm283x/Kconfig" -source "arch/arm/cpu/arm1176/bcm2835/Kconfig" +source "arch/arm/mach-davinci/Kconfig" source "arch/arm/cpu/armv7/exynos/Kconfig" @@ -842,8 +837,6 @@ source "board/palmtreo680/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/pxa255_idp/Kconfig" -source "board/raspberrypi/rpi/Kconfig" -source "board/raspberrypi/rpi_2/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 08946de244..bac3cb27e2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -5,6 +5,7 @@ # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. machine-$(CONFIG_ARCH_AT91) += at91 +machine-$(CONFIG_ARCH_BCM283X) += bcm283x machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 0667984b69..c005ce4905 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -19,9 +19,6 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \ PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -# Support generic board on ARM -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_CPPFLAGS += -D__ARM__ # Choose between ARM/Thumb instruction sets diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 1cfcca9fa6..1ec79a6f35 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -14,7 +14,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index 480e130489..deec427447 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -10,5 +10,3 @@ extra-y = start.o obj-y = cpu.o - -obj-$(CONFIG_BCM2835) += bcm2835/ diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig deleted file mode 100644 index 73cc72b411..0000000000 --- a/arch/arm/cpu/arm1176/bcm2835/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_RPI || TARGET_RPI_2 - -config DM - default y - -config DM_SERIAL - default y - -config DM_GPIO - default y - -endif diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index ac937bf5b0..4c0ab4d0ee 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -16,7 +16,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #ifndef CONFIG_SYS_PHY_UBOOT_BASE #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 01c85be64b..ec8e88d4b3 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -9,7 +9,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/hardware.h> /* diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 9b60436539..48abcd5260 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -22,7 +22,6 @@ #include <asm-offsets.h> #include <config.h> #include <common.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 8eb249475e..82cc1c9477 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -18,7 +18,6 @@ #include <asm-offsets.h> #include <config.h> #include <common.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 41123716a7..b55395aa53 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -17,7 +17,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 1312a9db9e..21fc03b97e 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -39,7 +39,6 @@ endif obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/ -obj-$(CONFIG_BCM2835) += bcm2835/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ diff --git a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S index 1febd7bac5..f4a701204b 100644 --- a/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S +++ b/arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S @@ -3,7 +3,6 @@ */ #include <config.h> -#include <version.h> #include <linux/linkage.h> ENTRY(save_boot_params) diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile deleted file mode 100644 index ed1ee4753d..0000000000 --- a/arch/arm/cpu/armv7/bcm2835/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2012 Stephen Warren -# -# SPDX-License-Identifier: GPL-2.0+ -# - -src_dir := ../../arm1176/bcm2835/ - -obj-y := -obj-y += $(src_dir)/init.o -obj-y += $(src_dir)/reset.o -obj-y += $(src_dir)/timer.o -obj-y += $(src_dir)/mbox.o diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index eb86a7fe7d..bd7540ac61 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -80,12 +80,6 @@ config DM_SPI_FLASH config DM_GPIO default y -config SYS_MALLOC_F - default y - -config SYS_MALLOC_F_LEN - default 0x400 - source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c index 31610909f8..584e4bac09 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c @@ -25,7 +25,6 @@ #include <common.h> #include <config.h> -#include <version.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clk.h> diff --git a/arch/arm/cpu/armv7/exynos/exynos4_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h index b633e56603..9f29d94c10 100644 --- a/arch/arm/cpu/armv7/exynos/exynos4_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos4_setup.h @@ -10,7 +10,6 @@ #define _ORIGEN_SETUP_H #include <config.h> -#include <version.h> #include <asm/arch/cpu.h> #ifdef CONFIG_CLK_800_330_165 diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 65da6e2c17..1f96498fb8 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -106,12 +106,6 @@ config DM_GPIO config DM_SERIAL default y if DM -config SYS_MALLOC_F - default y if DM - -config SYS_MALLOC_F_LEN - default 0x400 if DM - config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 7a691519bb..249761308e 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -12,7 +12,6 @@ */ #include <config.h> -#include <version.h> #include <asm/arch/mem.h> #include <asm/arch/clocks_omap3.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S index afed773c63..b4d0627871 100644 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -5,7 +5,6 @@ */ #include <config.h> -#include <version.h> /* Set up the platform, once the cpu has been initialized */ .globl lowlevel_init diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index bd9f338301..6a8c15d91f 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -8,7 +8,6 @@ #include <asm/io.h> #include <asm/u-boot.h> #include <asm/utils.h> -#include <version.h> #include <image.h> #include <asm/arch/reset_manager.h> #include <spl.h> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5050021e02..5ed0f45a26 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -15,7 +15,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/system.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 49f4032e9c..c3e04af36d 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -100,22 +100,23 @@ static struct { unsigned int freq; } pll1_para[] = { /* This array must be ordered by frequency. */ - { PLL1_CFG(16, 0, 0, 0), 384000000 }, - { PLL1_CFG(16, 1, 0, 0), 768000000 }, - { PLL1_CFG(20, 1, 0, 0), 960000000 }, - { PLL1_CFG(21, 1, 0, 0), 1008000000}, - { PLL1_CFG(22, 1, 0, 0), 1056000000}, - { PLL1_CFG(23, 1, 0, 0), 1104000000}, - { PLL1_CFG(24, 1, 0, 0), 1152000000}, - { PLL1_CFG(25, 1, 0, 0), 1200000000}, - { PLL1_CFG(26, 1, 0, 0), 1248000000}, - { PLL1_CFG(27, 1, 0, 0), 1296000000}, - { PLL1_CFG(28, 1, 0, 0), 1344000000}, - { PLL1_CFG(29, 1, 0, 0), 1392000000}, - { PLL1_CFG(30, 1, 0, 0), 1440000000}, { PLL1_CFG(31, 1, 0, 0), 1488000000}, - /* Final catchall entry */ - { PLL1_CFG(31, 1, 0, 0), ~0}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(19, 1, 0, 0), 912000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + /* Final catchall entry 384MHz*/ + { PLL1_CFG(16, 0, 0, 0), 0 }, + }; void clock_set_pll1(unsigned int hz) @@ -126,10 +127,12 @@ void clock_set_pll1(unsigned int hz) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* Find target frequency */ - while (pll1_para[i].freq < hz) + while (pll1_para[i].freq > hz) i++; hz = pll1_para[i].freq; + if (! hz) + hz = 384000000; /* Calculate system clock divisors */ axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S index 5be497b7be..e0a524e10c 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.S +++ b/arch/arm/cpu/armv7/sunxi/psci.S @@ -37,7 +37,7 @@ .arch_extension sec -#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000) +#define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000) #define TEN_MS (10 * ONE_MS) #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c index 14de9f98bd..524f25ce83 100644 --- a/arch/arm/cpu/armv7/sunxi/usbc.c +++ b/arch/arm/cpu/armv7/sunxi/usbc.c @@ -182,6 +182,13 @@ static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable) return; } +void sunxi_usbc_enable_squelch_detect(int index, int enable) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; + + usb_phy_write(sunxi_usbc, 0x3c, enable ? 0 : 2, 2); +} + int sunxi_usbc_request_resources(int index) { struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index]; diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index fa447bce16..d846236500 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -9,7 +9,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/macro.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S index b91a1b662f..baf9401e64 100644 --- a/arch/arm/cpu/armv8/exceptions.S +++ b/arch/arm/cpu/armv8/exceptions.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <asm/ptrace.h> #include <asm/macro.h> #include <linux/linkage.h> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index b4eab0b0f2..e5f2766a4a 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> #include <asm/armv8/mmu.h> diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S index f840b04df5..945445bc37 100644 --- a/arch/arm/cpu/armv8/tlb.S +++ b/arch/arm/cpu/armv8/tlb.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index ade1cdead8..253a39bd11 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> #include <linux/linkage.h> #include <asm/macro.h> diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index c77d51e6d8..879390be2d 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -21,7 +21,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 78e0cb8868..eebff661f8 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -11,7 +11,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> /* ************************************************************************* diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h index cb538cdc7d..133073321b 100644 --- a/arch/arm/include/asm/arch-sunxi/usbc.h +++ b/arch/arm/include/asm/arch-sunxi/usbc.h @@ -20,3 +20,4 @@ void sunxi_usbc_enable(int index); void sunxi_usbc_disable(int index); void sunxi_usbc_vbus_enable(int index); void sunxi_usbc_vbus_disable(int index); +void sunxi_usbc_enable_squelch_detect(int index, int enable); diff --git a/arch/arm/include/asm/semihosting.h b/arch/arm/include/asm/semihosting.h deleted file mode 100644 index 835ca7e4b6..0000000000 --- a/arch/arm/include/asm/semihosting.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2014 Broadcom Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SEMIHOSTING_H__ -#define __SEMIHOSTING_H__ - -/* - * ARM semihosting functions for loading images to memory. See the source - * code for more information. - */ -int smh_load(const char *fname, void *memp, int avail, int verbose); -long smh_len(const char *fname); - -#endif /* __SEMIHOSTING_H__ */ diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index fd6d8573f5..c3e964eabc 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -13,7 +13,7 @@ * for them. */ #include <common.h> -#include <asm/semihosting.h> +#include <command.h> #define SYSOPEN 0x01 #define SYSCLOSE 0x02 @@ -26,7 +26,7 @@ /* * Call the handler */ -static long smh_trap(unsigned int sysnum, void *addr) +static noinline long smh_trap(unsigned int sysnum, void *addr) { register long result asm("r0"); #if defined(CONFIG_ARM64) @@ -144,93 +144,71 @@ static long smh_len_fd(long fd) return ret; } -/* - * Open, load a file into memory, and close it. Check that the available space - * is sufficient to store the entire file. Return the bytes actually read from - * the file as seen by the read function. The verbose flag enables some extra - * printing of successful read status. - */ -int smh_load(const char *fname, void *memp, int avail, int verbose) +static int smh_load_file(const char * const name, ulong load_addr, + ulong *end_addr) { - long ret; long fd; - size_t len; - - ret = -1; - - debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname, - avail, memp); + long len; + long ret; - /* Open the file */ - fd = smh_open(fname, "rb"); + fd = smh_open(name, "rb"); if (fd == -1) return -1; - /* Get the file length */ - ret = smh_len_fd(fd); - if (ret == -1) { - smh_close(fd); - return -1; - } - - /* Check that the file will fit in the supplied buffer */ - if (ret > avail) { - printf("%s: ERROR ret %ld, avail %u\n", __func__, ret, - avail); + len = smh_len_fd(fd); + if (len < 0) { smh_close(fd); return -1; } - len = ret; + ret = smh_read(fd, (void *)load_addr, len); + smh_close(fd); - /* Read the file into the buffer */ - ret = smh_read(fd, memp, len); if (ret == 0) { - /* Print successful load information if requested */ - if (verbose) { - printf("\n%s\n", fname); - printf(" 0x%8p dest\n", memp); - printf(" 0x%08lx size\n", len); - printf(" 0x%08x avail\n", avail); - } + *end_addr = load_addr + len - 1; + printf("loaded file %s from %08lX to %08lX, %08lX bytes\n", + name, + load_addr, + *end_addr, + len); + } else { + printf("read failed\n"); + return 0; } - /* Close the file */ - smh_close(fd); - - return ret; + return 0; } -/* - * Get the file length from the filename - */ -long smh_len(const char *fname) +static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - long ret; - long fd; - long len; - - debug("%s: file \'%s\'\n", __func__, fname); - - /* Open the file */ - fd = smh_open(fname, "rb"); - if (fd < 0) - return fd; - - /* Get the file length */ - len = smh_len_fd(fd); - if (len < 0) { - smh_close(fd); - return len; + if (argc == 3 || argc == 4) { + ulong load_addr; + ulong end_addr = 0; + ulong ret; + char end_str[64]; + + load_addr = simple_strtoul(argv[2], NULL, 16); + if (!load_addr) + return -1; + + ret = smh_load_file(argv[1], load_addr, &end_addr); + if (ret < 0) + return 1; + + /* Optionally save returned end to the environment */ + if (argc == 4) { + sprintf(end_str, "0x%08lx", end_addr); + setenv(argv[3], end_str); + } + } else { + return CMD_RET_USAGE; } - - /* Close the file */ - ret = smh_close(fd); - if (ret < 0) - return ret; - - debug("%s: returning len %ld\n", __func__, len); - - /* Return the file length (or -1 error indication) */ - return len; + return 0; } + +U_BOOT_CMD(smhload, 4, 0, do_smhload, "load a file using semihosting", + "<file> 0x<address> [end var]\n" + " - load a semihosted file to the address specified\n" + " if the optional [end var] is specified, the end\n" + " address of the file will be stored in this environment\n" + " variable.\n"); diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig new file mode 100644 index 0000000000..b43f2d91fd --- /dev/null +++ b/arch/arm/mach-bcm283x/Kconfig @@ -0,0 +1,40 @@ +menu "Broadcom BCM283X family" + depends on ARCH_BCM283X + +choice + prompt "Broadcom BCM283X board select" + +config TARGET_RPI + bool "Raspberry Pi" + select CPU_ARM1176 + +config TARGET_RPI_2 + bool "Raspberry Pi 2" + select CPU_V7 + +endchoice + +config DM + default y + +config DM_SERIAL + default y + +config DM_GPIO + default y + +config SYS_BOARD + default "rpi" if TARGET_RPI + default "rpi_2" if TARGET_RPI_2 + +config SYS_VENDOR + default "raspberrypi" + +config SYS_SOC + default "bcm283x" + +config SYS_CONFIG_NAME + default "rpi" if TARGET_RPI + default "rpi_2" if TARGET_RPI_2 + +endmenu diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/mach-bcm283x/Makefile index 7e5dbe1fde..2505428bab 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/mach-bcm283x/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := lowlevel_init.o +obj-$(CONFIG_TARGET_RPI) += lowlevel_init.o obj-y += init.o reset.o timer.o mbox.o diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/mach-bcm283x/include/mach/gpio.h index c8ef8f528a..c8ef8f528a 100644 --- a/arch/arm/include/asm/arch-bcm2835/gpio.h +++ b/arch/arm/mach-bcm283x/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/mach-bcm283x/include/mach/mbox.h index 04bf480a54..04bf480a54 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/mach-bcm283x/include/mach/mbox.h diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/mach-bcm283x/include/mach/sdhci.h index 2a21ccbf66..2a21ccbf66 100644 --- a/arch/arm/include/asm/arch-bcm2835/sdhci.h +++ b/arch/arm/mach-bcm283x/include/mach/sdhci.h diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/mach-bcm283x/include/mach/timer.h index fc7aec7b7c..fc7aec7b7c 100644 --- a/arch/arm/include/asm/arch-bcm2835/timer.h +++ b/arch/arm/mach-bcm283x/include/mach/timer.h diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/mach-bcm283x/include/mach/wdog.h index beb6a08206..beb6a08206 100644 --- a/arch/arm/include/asm/arch-bcm2835/wdog.h +++ b/arch/arm/mach-bcm283x/include/mach/wdog.h diff --git a/arch/arm/cpu/arm1176/bcm2835/init.c b/arch/arm/mach-bcm283x/init.c index e90d3bba1f..e90d3bba1f 100644 --- a/arch/arm/cpu/arm1176/bcm2835/init.c +++ b/arch/arm/mach-bcm283x/init.c diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/mach-bcm283x/lowlevel_init.S index c7b0843281..c7b0843281 100644 --- a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S +++ b/arch/arm/mach-bcm283x/lowlevel_init.S diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/mach-bcm283x/mbox.c index 3b17a31eac..3b17a31eac 100644 --- a/arch/arm/cpu/arm1176/bcm2835/mbox.c +++ b/arch/arm/mach-bcm283x/mbox.c diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/mach-bcm283x/reset.c index 8c37ad9fd4..8c37ad9fd4 100644 --- a/arch/arm/cpu/arm1176/bcm2835/reset.c +++ b/arch/arm/mach-bcm283x/reset.c diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/mach-bcm283x/timer.c index 017907cfb8..017907cfb8 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/mach-bcm283x/timer.c diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fccfd79648..fce1c1dc87 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -17,9 +17,6 @@ config TEGRA124 endchoice -config SYS_MALLOC_F - default y - config SYS_MALLOC_F_LEN default 0x1800 diff --git a/arch/arm/mach-tegra/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S index a211bb3b1a..4bc0a3f5a1 100644 --- a/arch/arm/mach-tegra/lowlevel_init.S +++ b/arch/arm/mach-tegra/lowlevel_init.S @@ -8,7 +8,6 @@ */ #include <config.h> -#include <version.h> #include <linux/linkage.h> .align 5 diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 8335685e32..288e6aba79 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -1,9 +1,6 @@ menu "Panasonic UniPhier platform" depends on ARCH_UNIPHIER -config SYS_SOC - default "uniphier" - config SYS_CONFIG_NAME default "uniphier" @@ -48,12 +45,6 @@ config DCC_MICRO_SUPPORT_CARD endchoice -config SYS_MALLOC_F - default y - -config SYS_MALLOC_F_LEN - default 0x400 - config CMD_PINMON bool "Enable boot mode pins monitor command" default y diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index e7a801b2ac..24591d6ee5 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -12,6 +12,7 @@ obj-y += ddrphy_training.o else +obj-y += late_lowlevel_init.o obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o @@ -21,7 +22,6 @@ obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o obj-y += cache_uniphier.o -obj-$(CONFIG_UNIPHIER_SMP) += smp.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index 52f3c7c7a6..d8b8228853 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -119,36 +120,7 @@ void v7_outer_cache_disable(void) writel(tmp, SSCC); } -void wakeup_secondary(void); - void enable_caches(void) { - uint32_t reg; - -#ifdef CONFIG_UNIPHIER_SMP - /* - * The secondary CPU must move to DDR, - * before L2 disable. - * On SPL, the Page Table is located on the L2. - */ - wakeup_secondary(); -#endif - /* - * UniPhier SoCs must use L2 cache for init stack pointer. - * We disable L2 and L1 in this order. - * If CONFIG_SYS_DCACHE_OFF is not defined, - * caches are enabled again with a new page table. - */ - - /* L2 disable */ - v7_outer_cache_disable(); - - /* L1 disable */ - reg = get_cr(); - reg &= ~(CR_C | CR_M); - set_cr(reg); - -#ifndef CONFIG_SYS_DCACHE_OFF dcache_enable(); -#endif } diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S index 2638bcd779..ac2959a17d 100644 --- a/arch/arm/mach-uniphier/init_page_table.S +++ b/arch/arm/mach-uniphier/init_page_table.S @@ -1,3 +1,11 @@ +/* + * Copyright (C) 2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + #include <config.h> #include <linux/linkage.h> @@ -8,7 +16,7 @@ #define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */ #define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT)) -#define STACK_SECTION ((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT)) +#define STACK_SECTION ((CONFIG_SPL_STACK) >> (SECTION_SHIFT)) .section ".rodata" .align 14 diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S new file mode 100644 index 0000000000..1363364c80 --- /dev/null +++ b/arch/arm/mach-uniphier/late_lowlevel_init.S @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <mach/ssc-regs.h> + +ENTRY(lowlevel_init) + ldr r1, = SSCC + ldr r0, [r1] + bic r0, r0, #SSCC_ON @ L2 disable + str r0, [r1] + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 92299fe64d..825b160762 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -1,6 +1,7 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -24,8 +25,8 @@ ENTRY(lowlevel_init) * First we need to turn on MMU and Dcache again to get back * data access to L2. */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) - orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) + orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 #ifdef CONFIG_DEBUG_LL @@ -40,13 +41,32 @@ ENTRY(lowlevel_init) ldr r3, =init_page_table @ page table must be 16KB aligned /* Disable MMU and Dcache before switching Page Table */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 bl enable_mmu #ifdef CONFIG_UNIPHIER_SMP +secondary_startup: + /* + * Entry point for secondary CPUs + * + * The Boot ROM has already enabled MMU for the secondary CPUs as well + * as for the primary one. The MMU table embedded in the Boot ROM + * prohibits the DRAM access, so it is impossible to bring the + * secondary CPUs into DRAM directly. They must jump here into SPL, + * which is run on L2 cache. + * + * Boot Sequence + * [primary CPU] [secondary CPUs] + * start from Boot ROM start from Boot ROM + * jump to SPL sleep in Boot ROM + * kick secondaries ---(sev)---> jump to SPL + * jump to U-Boot main sleep in SPL + * jump to Linux + * kick secondaries ---(sev)---> jump to Linux + */ /* * ACTLR (Auxiliary Control Register) for Cortex-A9 * bit[9] Parity on @@ -54,7 +74,7 @@ ENTRY(lowlevel_init) * bit[7] EXCL (Exclusive cache bit) * bit[6] SMP * bit[3] Write full line of zeros mode - * bit[2] L1 Prefetch enable + * bit[2] L1 prefetch enable * bit[1] L2 prefetch enable * bit[0] FW (Cache and TLB maintenance broadcast) */ @@ -67,20 +87,31 @@ ENTRY(lowlevel_init) and r0, r0, #0x3 cmp r0, #0x0 beq primary_cpu - ldr r1, =ROM_BOOT_ROMRSV2 + /* only for secondary CPUs */ + ldr r1, =ROM_BOOT_ROMRSV2 @ The last data access to L2 cache + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) + orr r0, r0, #CR_I @ Enable ICache + bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache must be disabled + mcr p15, 0, r0, c1, c0, 0 @ before jumping to Linux mov r0, #0 str r0, [r1] -0: wfe - ldr r0, [r1] + b 1f + /* + * L2 cache is shared among all the CPUs and it might be disabled by + * the primary one. Before that, the following 5 lines must be cached + * on the Icaches of the secondary CPUs. + */ +0: wfe @ kicked by Linux +1: ldr r0, [r1] cmp r0, #0 - beq 0b - bx r0 @ r0: entry point of U-Boot main for the secondary CPU + bxne r0 @ r0: Linux entry for secondary CPUs + b 0b primary_cpu: ldr r1, =ROM_BOOT_ROMRSV2 - ldr r0, =_start @ entry for the secondary CPU + ldr r0, =secondary_startup str r0, [r1] ldr r0, [r1] @ make sure str is complete before sev - sev @ kick the sedoncary CPU + sev @ kick the secondary CPU mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register bfc r1, #0, #13 @ clear bit 12-0 mov r0, #-1 @@ -117,7 +148,7 @@ ENTRY(enable_mmu) * TLBs was already invalidated in "../start.S" * So, we don't need to invalidate it here. */ - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable mcr p15, 0, r0, c1, c0, 0 @@ -142,7 +173,7 @@ ENTRY(setup_init_ram) ldr r0, = 0x00408006 @ touch to zero with address range ldr r1, = SSCOQM str r0, [r1] - ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address + ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address ldr r1, = SSCOQAD str r0, [r1] ldr r0, = BOOT_RAM_SIZE @@ -154,7 +185,7 @@ ENTRY(setup_init_ram) ldr r1, = SSCOPPQSEF ldr r0, [r1] cmp r0, #0 @ check if the command is successfully set - bne 0b @ try again if an error occurres + bne 0b @ try again if an error occurs ldr r1, = SSCOLPQS 1: diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile index 5ce3d8a520..af815c3260 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/Makefile +++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile @@ -5,12 +5,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o + early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_SPL_DM) += platdevice.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c new file mode 100644 index 0000000000..e5e86bb363 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ + sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ + + sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ + sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ + + sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ + sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c index 15d81ebb3d..3074d0a8d2 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -14,20 +14,6 @@ void pin_init(void) /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ - sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ - - sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ - sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ - - sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ - sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ - - sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ - sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ -#endif - #ifdef CONFIG_NAND_DENALI sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */ sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */ diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile index b88525c82d..f6a584e1f0 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/Makefile +++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile @@ -5,12 +5,12 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o + early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o +obj-$(CONFIG_SPL_DM) += platdevice.o else obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o endif obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c new file mode 100644 index 0000000000..85bb6a0b9c --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ + sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ + sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ + sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ + sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ + sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ + sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c index f382ef4842..4df9098ef0 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -12,17 +12,6 @@ void pin_init(void) { /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ - sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ - sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ - sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ - sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ - sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ - sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ - sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ -#endif - #ifdef CONFIG_NAND_DENALI sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */ sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */ diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile index 5ce3d8a520..8eb575e1d3 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/Makefile +++ b/arch/arm/mach-uniphier/ph1-sld8/Makefile @@ -1,16 +1 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o -obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o -obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o -endif - -obj-y += boot-mode.o +include $(src)/../ph1-ld4/Makefile diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c new file mode 100644 index 0000000000..28cc4296fc --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ + sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ + + sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ + + sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ + sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c index 4c494ffa40..57a8093048 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h> @@ -12,20 +12,6 @@ void pin_init(void) { /* Comment format: PAD Name -> Function Name */ -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ - sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ - - sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ - sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ - - sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ - sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ - - sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ - sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ -#endif - #ifdef CONFIG_SYS_I2C_UNIPHIER { u32 tmp; diff --git a/arch/arm/mach-uniphier/smp.S b/arch/arm/mach-uniphier/smp.S deleted file mode 100644 index 18e3a9d21e..0000000000 --- a/arch/arm/mach-uniphier/smp.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2013 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/linkage.h> -#include <asm/system.h> -#include <mach/led.h> -#include <mach/sbc-regs.h> - -/* Entry point of U-Boot main program for the secondary CPU */ -LENTRY(secondary_entry) - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) - bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable - mcr p15, 0, r0, c1, c0, 0 - mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs - mcr p15, 0, r0, c7, c5, 0 @ invalidate icache - dsb - led_write(C,0,,) - ldr r1, =ROM_BOOT_ROMRSV2 - mov r0, #0 - str r0, [r1] -0: wfe - ldr r4, [r1] @ r4: entry point for secondary CPUs - cmp r4, #0 - beq 0b - led_write(C, P, U, 1) - bx r4 @ secondary CPUs jump to linux -ENDPROC(secondary_entry) - -ENTRY(wakeup_secondary) - ldr r1, =ROM_BOOT_ROMRSV2 -0: ldr r0, [r1] - cmp r0, #0 - bne 0b - - /* set entry address and send event to the secondary CPU */ - ldr r0, =secondary_entry - str r0, [r1] - ldr r0, [r1] @ make sure store is complete - mov r0, #0x100 -0: subs r0, r0, #1 @ I don't know the reason, but without this wait - bne 0b @ fails to wake up the secondary CPU - sev - - /* wait until the secondary CPU reach to secondary_entry */ -0: ldr r0, [r1] - cmp r0, #0 - bne 0b - bx lr -ENDPROC(wakeup_secondary) diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c index c3d90d03d0..a34d3a167c 100644 --- a/arch/arm/mach-uniphier/spl.c +++ b/arch/arm/mach-uniphier/spl.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2013-2015 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -20,6 +21,7 @@ void pll_init(void); void pin_init(void); void memconf_init(void); void early_clkrst_init(void); +void early_pin_init(void); int umc_init(void); void enable_dpll_ssc(void); @@ -47,6 +49,16 @@ void spl_board_init(void) led_write(L, 2, , ); + early_pin_init(); + + led_write(L, 3, , ); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_write(L, 4, , ); + { int res; @@ -56,9 +68,9 @@ void spl_board_init(void) ; } } - led_write(L, 3, , ); + led_write(L, 5, , ); enable_dpll_ssc(); - led_write(L, 4, , ); + led_write(L, 6, , ); } diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c index e7b4158636..77cc794e61 100644 --- a/arch/arm/mach-uniphier/support_card.c +++ b/arch/arm/mach-uniphier/support_card.c @@ -1,6 +1,7 @@ /* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -94,7 +95,7 @@ void support_card_init(void) /* * After power on, we need to keep the LAN controller in reset state * for a while. (200 usec) - * Fortunatelly, enough wait time is already inserted in pll_init() + * Fortunately, enough wait time is already inserted in pll_init() * function. So we do not have to wait here. */ support_card_reset_deassert(); @@ -213,11 +214,11 @@ static void detect_num_flash_banks(void) debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); } -#else /* ONFIG_SYS_NO_FLASH */ +#else /* CONFIG_SYS_NO_FLASH */ void detect_num_flash_banks(void) { }; -#endif /* ONFIG_SYS_NO_FLASH */ +#endif /* CONFIG_SYS_NO_FLASH */ void support_card_late_init(void) { diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 8252f598c3..469185e8b4 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -9,9 +9,6 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := avr32-linux- endif -# avr32 has generic board support -__HAVE_ARCH_GENERIC_BOARD := y - CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 584b38b17a..7b17b75743 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -20,9 +20,6 @@ CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%)) endif CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%)) -# Support generic board on Blackfin -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic LDFLAGS_FINAL += --gc-sections diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 73cbfa2cc8..d2cf71bfaf 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -174,7 +174,6 @@ } #endif -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_CPUINFO #define CONFIG_ARCH_MISC_INIT diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 53c4aabe1e..69cb0f73eb 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -4,71 +4,200 @@ menu "M68000 architecture" config SYS_ARCH default "m68k" +# processor family +config MCF520x + bool + +config MCF52x2 + bool + +config MCF523x + bool + +config MCF530x + bool + +config MCF5301x + bool + +config MCF532x + bool + +config MCF537x + bool + +config MCF5441x + bool + +config MCF5445x + bool + +config MCF5227x + bool + +config MCF547x_8x + bool + +# processor type +config M5208 + bool + select MCF520x + +config M5235 + bool + select MCF523x + +config M5249 + bool + select MCF52x2 + +config M5253 + bool + select MCF52x2 + +config M5271 + bool + select MCF52x2 + +config M5272 + bool + select MCF52x2 + +config M5275 + bool + select MCF52x2 + +config M5282 + bool + select MCF52x2 + +config M5307 + bool + select MCF530x + +config M53015 + bool + select MCF5301x + +config M5329 + bool + select MCF532x + +config M5373 + bool + select MCF532x + select MCF537x + +config M54418 + bool + select MCF5441x + +config M54451 + bool + select MCF5445x + +config M54455 + bool + select MCF5445x + +config M52277 + bool + select MCF5227x + +config M547x + bool + select MCF547x_8x + +config M548x + bool + select MCF547x_8x + choice prompt "Target select" config TARGET_M52277EVB bool "Support M52277EVB" + select M52277 config TARGET_M5235EVB bool "Support M5235EVB" + select M5235 config TARGET_COBRA5272 bool "Support cobra5272" + select M5272 config TARGET_EB_CPU5282 bool "Support eb_cpu5282" + select M5282 config TARGET_M5208EVBE bool "Support M5208EVBE" + select M5208 config TARGET_M5249EVB bool "Support M5249EVB" + select M5249 config TARGET_M5253DEMO bool "Support M5253DEMO" + select M5253 config TARGET_M5253EVBE bool "Support M5253EVBE" + select M5253 config TARGET_M5272C3 bool "Support M5272C3" + select M5272 config TARGET_M5275EVB bool "Support M5275EVB" + select M5275 config TARGET_M5282EVB bool "Support M5282EVB" + select M5282 config TARGET_ASTRO_MCF5373L bool "Support astro_mcf5373l" + select M5373 config TARGET_M53017EVB bool "Support M53017EVB" + select M53015 config TARGET_M5329EVB bool "Support M5329EVB" + select M5329 config TARGET_M5373EVB bool "Support M5373EVB" + select M5373 config TARGET_M54418TWR bool "Support M54418TWR" + select M54418 config TARGET_M54451EVB bool "Support M54451EVB" + select M54451 config TARGET_M54455EVB bool "Support M54455EVB" + select M54455 config TARGET_M5475EVB bool "Support M5475EVB" + select M547x config TARGET_M5485EVB bool "Support M5485EVB" + select M548x config TARGET_AMCORE bool "Support AMCORE" + select M5307 endchoice diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index aa3d2fae63..e6f3b482c3 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -6,3 +6,32 @@ head-y := arch/m68k/cpu/$(CPU)/start.o libs-y += arch/m68k/cpu/$(CPU)/ libs-y += arch/m68k/lib/ + +cpuflags-$(CONFIG_M5208) := -mcpu=5208 +cpuflags-$(CONFIG_M5235) := -mcpu=5235 -fPIC +cpuflags-$(CONFIG_M52277) := -mcpu=52277 -fPIC +cpuflags-$(CONFIG_M5249) := -mcpu=5249 +cpuflags-$(CONFIG_M5253) := -mcpu=5253 +cpuflags-$(CONFIG_M5271) := -mcpu=5271 +cpuflags-$(CONFIG_M5272) := -mcpu=5272 +cpuflags-$(CONFIG_M5275) := -mcpu=5275 +cpuflags-$(CONFIG_M5282) := -mcpu=5282 +cpuflags-$(CONFIG_M5307) := -mcpu=5307 +cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC +cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC +cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC +cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC +cpuflags-$(CONFIG_MCF547x_8x) := -mcpu=5485 -fPIC + +PLATFORM_CPPFLAGS += $(cpuflags-y) + + +ldflags-$(CONFIG_MCF5441x) := --got=single +ldflags-$(CONFIG_MCF5445x) := --got=single +ldflags-$(CONFIG_MCF547x_8x) := --got=single + +ifneq (,$(findstring -linux-,$(shell $(CC) --version))) +ifneq (,$(findstring GOT,$(shell $(LD) --help))) +PLATFORM_LDFLAGS += $(ldflags-y) +endif +endif diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index a629b68d61..3b3a7e88ab 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -11,9 +11,6 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 -# Support generic board on m68k -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_CPPFLAGS += -D__M68K__ PLATFORM_LDFLAGS += -n PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/m68k/cpu/mcf5227x/config.mk b/arch/m68k/cpu/mcf5227x/config.mk deleted file mode 100644 index b5c26e4e5b..0000000000 --- a/arch/m68k/cpu/mcf5227x/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mcpu=52277 -fPIC diff --git a/arch/m68k/cpu/mcf523x/config.mk b/arch/m68k/cpu/mcf523x/config.mk deleted file mode 100644 index c9435ab99b..0000000000 --- a/arch/m68k/cpu/mcf523x/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mcpu=5235 -fPIC diff --git a/arch/m68k/cpu/mcf52x2/config.mk b/arch/m68k/cpu/mcf52x2/config.mk deleted file mode 100644 index f66000b331..0000000000 --- a/arch/m68k/cpu/mcf52x2/config.mk +++ /dev/null @@ -1,39 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is5208:=$(shell grep CONFIG_M5208 $(cfg)) -is5249:=$(shell grep CONFIG_M5249 $(cfg)) -is5253:=$(shell grep CONFIG_M5253 $(cfg)) -is5271:=$(shell grep CONFIG_M5271 $(cfg)) -is5272:=$(shell grep CONFIG_M5272 $(cfg)) -is5275:=$(shell grep CONFIG_M5275 $(cfg)) -is5282:=$(shell grep CONFIG_M5282 $(cfg)) - -ifneq (,$(findstring CONFIG_M5208,$(is5208))) -PLATFORM_CPPFLAGS += -mcpu=5208 -endif -ifneq (,$(findstring CONFIG_M5249,$(is5249))) -PLATFORM_CPPFLAGS += -mcpu=5249 -endif -ifneq (,$(findstring CONFIG_M5253,$(is5253))) -PLATFORM_CPPFLAGS += -mcpu=5253 -endif -ifneq (,$(findstring CONFIG_M5271,$(is5271))) -PLATFORM_CPPFLAGS += -mcpu=5271 -endif -ifneq (,$(findstring CONFIG_M5272,$(is5272))) -PLATFORM_CPPFLAGS += -mcpu=5272 -endif -ifneq (,$(findstring CONFIG_M5275,$(is5275))) -PLATFORM_CPPFLAGS += -mcpu=5275 -endif -ifneq (,$(findstring CONFIG_M5282,$(is5282))) -PLATFORM_CPPFLAGS += -mcpu=5282 -endif diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk deleted file mode 100644 index aef72d70c5..0000000000 --- a/arch/m68k/cpu/mcf530x/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is5307:=$(shell grep CONFIG_M5307 $(cfg)) - -ifneq (,$(findstring CONFIG_M5307,$(is5307))) -PLATFORM_CPPFLAGS += -mcpu=5307 -endif diff --git a/arch/m68k/cpu/mcf532x/config.mk b/arch/m68k/cpu/mcf532x/config.mk deleted file mode 100644 index 2efb60f04a..0000000000 --- a/arch/m68k/cpu/mcf532x/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is5301x:=$(shell grep CONFIG_MCF5301x $(cfg)) -is532x:=$(shell grep CONFIG_MCF532x $(cfg)) - -ifneq (,$(findstring CONFIG_MCF5301x,$(is5301x))) -PLATFORM_CPPFLAGS += -mcpu=53015 -fPIC -endif -ifneq (,$(findstring CONFIG_MCF532x,$(is532x))) -PLATFORM_CPPFLAGS += -mcpu=5329 -fPIC -endif diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk deleted file mode 100644 index 13f8a9f57b..0000000000 --- a/arch/m68k/cpu/mcf5445x/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright 2011-2012 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is5441x:=$(shell grep CONFIG_MCF5441x $(cfg)) - -ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x))) -PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC -else -PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC -endif - -ifneq (,$(findstring -linux-,$(shell $(CC) --version))) -ifneq (,$(findstring GOT,$(shell $(LD) --help))) -PLATFORM_LDFLAGS += --got=single -endif -endif diff --git a/arch/m68k/cpu/mcf547x_8x/config.mk b/arch/m68k/cpu/mcf547x_8x/config.mk deleted file mode 100644 index 825f6ccebe..0000000000 --- a/arch/m68k/cpu/mcf547x_8x/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC - -ifneq (,$(findstring -linux-,$(shell $(CC) --version))) -ifneq (,$(findstring GOT,$(shell $(LD) --help))) -PLATFORM_LDFLAGS += --got=single -endif -endif diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index 7590842881..e1458acd2c 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_GLOBAL_DATA #define CONFIG_NEEDS_MANUAL_RELOC diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index d0e1a845dd..73d40bda8b 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -5,9 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifndef CONFIG_SYS_GENERIC_BOARD -obj-y += board.o -endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += interrupts.o diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c deleted file mode 100644 index 9caff73505..0000000000 --- a/arch/m68k/lib/board.c +++ /dev/null @@ -1,642 +0,0 @@ -/* - * (C) Copyright 2003 - * Josef Baumgartner <josef.baumgartner@telex.de> - * - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <watchdog.h> -#include <command.h> -#include <malloc.h> -#include <stdio_dev.h> -#include <linux/compiler.h> - -#include <asm/immap.h> - -#if defined(CONFIG_CMD_IDE) -#include <ide.h> -#endif -#if defined(CONFIG_CMD_SCSI) -#include <scsi.h> -#endif -#if defined(CONFIG_CMD_KGDB) -#include <kgdb.h> -#endif -#ifdef CONFIG_STATUS_LED -#include <status_led.h> -#endif -#include <net.h> -#include <serial.h> -#ifdef CONFIG_SYS_ALLOC_DPRAM -#include <commproc.h> -#endif -#include <version.h> - -#if defined(CONFIG_HARD_I2C) || \ - defined(CONFIG_SYS_I2C) -#include <i2c.h> -#endif - -#ifdef CONFIG_CMD_SPI -#include <spi.h> -#endif - -#ifdef CONFIG_BITBANGMII -#include <miiphy.h> -#endif - -#include <nand.h> - -DECLARE_GLOBAL_DATA_PTR; - -static char *failed = "*** failed ***\n"; - -#include <environment.h> - -extern ulong __init_end; -extern ulong __bss_end; - -#if defined(CONFIG_WATCHDOG) -# undef INIT_FUNC_WATCHDOG_INIT -# define INIT_FUNC_WATCHDOG_INIT watchdog_init, -# define WATCHDOG_DISABLE watchdog_disable - -extern int watchdog_init(void); -extern int watchdog_disable(void); -#else -# define INIT_FUNC_WATCHDOG_INIT /* undef */ -# define WATCHDOG_DISABLE /* undef */ -#endif /* CONFIG_WATCHDOG */ - -ulong monitor_flash_len; - -/************************************************************************ - * Utilities * - ************************************************************************ - */ - -/* - * All attempts to come up with a "common" initialization sequence - * that works for all boards and architectures failed: some of the - * requirements are just _too_ different. To get rid of the resulting - * mess of board dependend #ifdef'ed code we now make the whole - * initialization sequence configurable to the user. - * - * The requirements for any new initalization function is simple: it - * receives a pointer to the "global data" structure as it's only - * argument, and returns an integer return code, where 0 means - * "continue" and != 0 means "fatal error, hang the system". - */ -typedef int (init_fnc_t) (void); - -/************************************************************************ - * Init Utilities - ************************************************************************ - * Some of this code should be moved into the core functions, - * but let's get it working (again) first... - */ - -static int init_baudrate (void) -{ - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - return 0; -} - -/***********************************************************************/ - -static int init_func_ram (void) -{ - int board_type = 0; /* use dummy arg */ - puts ("DRAM: "); - - if ((gd->ram_size = initdram (board_type)) > 0) { - print_size (gd->ram_size, "\n"); - return (0); - } - puts (failed); - return (1); -} - -/***********************************************************************/ - -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) -static int init_func_i2c (void) -{ - puts ("I2C: "); -#ifdef CONFIG_SYS_I2C - i2c_init_all(); -#else - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - puts ("ready\n"); - return (0); -} -#endif - -#if defined(CONFIG_HARD_SPI) -static int init_func_spi (void) -{ - puts ("SPI: "); - spi_init (); - puts ("ready\n"); - return (0); -} -#endif - -/***********************************************************************/ - -/************************************************************************ - * Initialization sequence * - ************************************************************************ - */ - -init_fnc_t *init_sequence[] = { - get_clocks, - env_init, - init_baudrate, - serial_init, - console_init_f, - display_options, - checkcpu, - checkboard, -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) - init_func_i2c, -#endif -#if defined(CONFIG_HARD_SPI) - init_func_spi, -#endif - init_func_ram, -#if defined(CONFIG_SYS_DRAM_TEST) - testdram, -#endif /* CONFIG_SYS_DRAM_TEST */ - INIT_FUNC_WATCHDOG_INIT - NULL, /* Terminate this list */ -}; - - -/************************************************************************ - * - * This is the first part of the initialization sequence that is - * implemented in C, but still running from ROM. - * - * The main purpose is to provide a (serial) console interface as - * soon as possible (so we can see any error messages), and to - * initialize the RAM so that we can relocate the monitor code to - * RAM. - * - * Be aware of the restrictions: global data is read-only, BSS is not - * initialized, and stack space is limited to a few kB. - * - ************************************************************************ - */ - -void -board_init_f (ulong bootflag) -{ - bd_t *bd; - ulong len, addr, addr_sp; - ulong *paddr; - gd_t *id; - init_fnc_t **init_fnc_ptr; -#ifdef CONFIG_PRAM - ulong reg; -#endif - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr)() != 0) { - hang (); - } - } - - /* - * Now that we have DRAM mapped and working, we can - * relocate the code and continue running from DRAM. - * - * Reserve memory at end of RAM for (top down in that order): - * - protected RAM - * - LCD framebuffer - * - monitor code - * - board info struct - */ - len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; - - addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; - -#ifdef CONFIG_LOGBUFFER - /* reserve kernel log buffer */ - addr -= (LOGBUFF_RESERVE); - debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); -#endif - -#ifdef CONFIG_PRAM - /* - * reserve protected RAM - */ - reg = getenv_ulong("pram", 10, CONFIG_PRAM); - addr -= (reg << 10); /* size is in kB */ - debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); -#endif /* CONFIG_PRAM */ - - /* round down to next 4 kB limit */ - addr &= ~(4096 - 1); - debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); - -#ifdef CONFIG_LCD -#ifdef CONFIG_FB_ADDR - gd->fb_base = CONFIG_FB_ADDR; -#else - /* reserve memory for LCD display (always full pages) */ - addr = lcd_setmem (addr); - gd->fb_base = addr; -#endif /* CONFIG_FB_ADDR */ -#endif /* CONFIG_LCD */ - - /* - * reserve memory for U-Boot code, data & bss - * round down to next 4 kB limit - */ - addr -= len; - addr &= ~(4096 - 1); - - debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); - - /* - * reserve memory for malloc() arena - */ - addr_sp = addr - TOTAL_MALLOC_LEN; - debug ("Reserving %dk for malloc() at: %08lx\n", - TOTAL_MALLOC_LEN >> 10, addr_sp); - - /* - * (permanently) allocate a Board Info struct - * and a permanent copy of the "global" data - */ - addr_sp -= sizeof (bd_t); - bd = (bd_t *) addr_sp; - gd->bd = bd; - debug ("Reserving %zu Bytes for Board Info at: %08lx\n", - sizeof (bd_t), addr_sp); - addr_sp -= sizeof (gd_t); - id = (gd_t *) addr_sp; - debug ("Reserving %zu Bytes for Global Data at: %08lx\n", - sizeof (gd_t), addr_sp); - - /* Reserve memory for boot params. */ - addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN; - bd->bi_boot_params = addr_sp; - debug ("Reserving %dk for boot parameters at: %08lx\n", - CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp); - - /* - * Finally, we set up a new (bigger) stack. - * - * Leave some safety gap for SP, force alignment on 16 byte boundary - * Clear initial stack frame - */ - addr_sp -= 16; - addr_sp &= ~0xF; - - paddr = (ulong *)addr_sp; - *paddr-- = 0; - *paddr-- = 0; - addr_sp = (ulong)paddr; - - debug ("Stack Pointer at: %08lx\n", addr_sp); - - /* - * Save local variables to board info struct - */ - bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */ - bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ -#ifdef CONFIG_SYS_INIT_RAM_ADDR - bd->bi_sramstart = CONFIG_SYS_INIT_RAM_ADDR; /* start of SRAM memory */ - bd->bi_sramsize = CONFIG_SYS_INIT_RAM_SIZE; /* size of SRAM memory */ -#endif - bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ - - bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ - - WATCHDOG_RESET (); - bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ - bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ -#ifdef CONFIG_PCI - bd->bi_pcifreq = gd->pci_clk; /* PCI Freq in Hz */ -#endif -#ifdef CONFIG_EXTRA_CLOCK - bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ - bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ - bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ -#endif - -#ifdef CONFIG_SYS_EXTBDINFO - strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); - strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version)); -#endif - - WATCHDOG_RESET (); - -#ifdef CONFIG_POST - post_bootmode_init(); - post_run (NULL, POST_ROM | post_bootmode_get(0)); -#endif - - WATCHDOG_RESET(); - - memcpy (id, (void *)gd, sizeof (gd_t)); - - debug ("Start relocate of code from %08x to %08lx\n", CONFIG_SYS_MONITOR_BASE, addr); - relocate_code (addr_sp, id, addr); - - /* NOTREACHED - jump_to_ram() does not return */ -} - -/************************************************************************ - * - * This is the next part if the initialization sequence: we are now - * running from RAM and have a "normal" C environment, i. e. global - * data can be written, BSS has been cleared, the stack size in not - * that critical any more, etc. - * - ************************************************************************ - */ -void board_init_r (gd_t *id, ulong dest_addr) -{ - char *s __maybe_unused; - bd_t *bd; - -#ifndef CONFIG_ENV_IS_NOWHERE - extern char * env_name_spec; -#endif -#ifndef CONFIG_SYS_NO_FLASH - ulong flash_size; -#endif - gd = id; /* initialize RAM version of global data */ - bd = gd->bd; - - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - - WATCHDOG_RESET (); - - gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; - - serial_initialize(); - - debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); - - monitor_flash_len = (ulong)&__init_end - dest_addr; - -#if defined(CONFIG_NEEDS_MANUAL_RELOC) - /* - * We have to relocate the command table manually - */ - fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd), - ll_entry_count(cmd_tbl_t, cmd)); -#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */ - - /* there are some other pointer constants we must deal with */ -#ifndef CONFIG_ENV_IS_NOWHERE - env_name_spec += gd->reloc_off; -#endif - - WATCHDOG_RESET (); - -#ifdef CONFIG_LOGBUFFER - logbuff_init_ptrs (); -#endif -#ifdef CONFIG_POST - post_output_backlog (); - post_reloc (); -#endif - WATCHDOG_RESET(); - -#if 0 - /* instruction cache enabled in cpu_init_f() for faster relocation */ - icache_enable (); /* it's time to enable the instruction cache */ -#endif - - /* - * Setup trap handlers - */ - trap_init (CONFIG_SYS_SDRAM_BASE); - - /* The Malloc area is immediately below the monitor copy in DRAM */ - mem_malloc_init (CONFIG_SYS_MONITOR_BASE + gd->reloc_off - - TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN); - -#if !defined(CONFIG_SYS_NO_FLASH) - puts ("Flash: "); - - if ((flash_size = flash_init ()) > 0) { -# ifdef CONFIG_SYS_FLASH_CHECKSUM - print_size (flash_size, ""); - /* - * Compute and print flash CRC if flashchecksum is set to 'y' - * - * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX - */ - if (getenv_yesno("flashchecksum") == 1) { - printf (" CRC: %08X", - crc32 (0, - (const unsigned char *) CONFIG_SYS_FLASH_BASE, - flash_size) - ); - } - putc ('\n'); -# else /* !CONFIG_SYS_FLASH_CHECKSUM */ - print_size (flash_size, "\n"); -# endif /* CONFIG_SYS_FLASH_CHECKSUM */ - } else { - puts (failed); - hang (); - } - - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */ - bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */ - bd->bi_flashoffset = 0; -#else /* CONFIG_SYS_NO_FLASH */ - bd->bi_flashsize = 0; - bd->bi_flashstart = 0; - bd->bi_flashoffset = 0; -#endif /* !CONFIG_SYS_NO_FLASH */ - - WATCHDOG_RESET (); - - /* initialize higher level parts of CPU like time base and timers */ - cpu_init_r (); - - WATCHDOG_RESET (); - -#ifdef CONFIG_SPI -# if !defined(CONFIG_ENV_IS_IN_EEPROM) - spi_init_f (); -# endif - spi_init_r (); -#endif - -#if defined(CONFIG_SYS_I2C) - /* Adjust I2C subsystem pointers after relocation */ - i2c_reloc_fixup(); -#endif - - /* relocate environment function pointers etc. */ - env_relocate (); - - WATCHDOG_RESET (); - -#if defined(CONFIG_PCI) - /* - * Do pci configuration - */ - pci_init (); -#endif - - /** leave this here (after malloc(), environment and PCI are working) **/ - /* Initialize stdio devices */ - stdio_init (); - - /* Initialize the jump table for applications */ - jumptable_init (); - - /* Initialize the console (after the relocation and devices init) */ - console_init_r (); - -#if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r (); -#endif - -#if defined(CONFIG_CMD_KGDB) - WATCHDOG_RESET (); - puts ("KGDB: "); - kgdb_init (); -#endif - - debug ("U-Boot relocated to %08lx\n", dest_addr); - - /* - * Enable Interrupts - */ - interrupt_init (); - - /* Must happen after interrupts are initialized since - * an irq handler gets installed - */ - timer_init(); - -#ifdef CONFIG_STATUS_LED - status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); -#endif - - udelay (20); - - /* Insert function pointers now that we have relocated the code */ - - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - - WATCHDOG_RESET (); - -#if defined(CONFIG_CMD_DOC) - WATCHDOG_RESET (); - puts ("DOC: "); - doc_init (); -#endif - -#if defined(CONFIG_CMD_NAND) - WATCHDOG_RESET (); - puts ("NAND: "); - nand_init(); /* go init the NAND */ -#endif - -#ifdef CONFIG_BITBANGMII - bb_miiphy_init(); -#endif -#if defined(CONFIG_CMD_NET) - WATCHDOG_RESET(); -#if defined(FEC_ENET) - eth_init(bd); -#endif - puts ("Net: "); - eth_initialize (bd); -#endif - -#ifdef CONFIG_POST - post_run (NULL, POST_RAM | post_bootmode_get(0)); -#endif - -#if defined(CONFIG_CMD_PCMCIA) \ - && !defined(CONFIG_CMD_IDE) - WATCHDOG_RESET (); - puts ("PCMCIA:"); - pcmcia_init (); -#endif - -#if defined(CONFIG_CMD_IDE) - WATCHDOG_RESET (); - puts ("IDE: "); - ide_init (); -#endif - -#ifdef CONFIG_LAST_STAGE_INIT - WATCHDOG_RESET (); - /* - * Some parts can be only initialized if all others (like - * Interrupts) are up and running (i.e. the PC-style ISA - * keyboard). - */ - last_stage_init (); -#endif - -#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) - /* - * Export available size of memory for Linux, - * taking into account the protected RAM at top of memory - */ - { - ulong pram = 0; - char memsz[32]; - -#ifdef CONFIG_PRAM - pram = getenv_ulong("pram", 10, CONFIG_PRAM); -#endif -#ifdef CONFIG_LOGBUFFER - /* Also take the logbuffer into account (pram is in kB) */ - pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; -#endif - sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram); - setenv ("mem", memsz); - } -#endif - -#ifdef CONFIG_WATCHDOG - /* disable watchdog if environment is set */ - if ((s = getenv ("watchdog")) != NULL) { - if (strncmp (s, "off", 3) == 0) { - WATCHDOG_DISABLE (); - } - } -#endif /* CONFIG_WATCHDOG*/ - - - /* Initialization complete - start the monitor */ - - /* main_loop() can return to retry autoboot, if so just run it again. */ - for (;;) { - WATCHDOG_RESET (); - main_loop (); - } - - /* NOTREACHED - no way out of command loop except booting */ -} diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 2b817be61a..e7a347738a 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -19,4 +19,3 @@ PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ ifeq ($(CONFIG_SPL_BUILD),) PLATFORM_CPPFLAGS += -fPIC endif -__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index 2cc0a2da89..f4bb0915c5 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -9,7 +9,6 @@ #include <common.h> #include <image.h> #include <spl.h> -#include <version.h> #include <asm/io.h> #include <asm/u-boot.h> diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h index 32fd636b61..4af408a761 100644 --- a/arch/microblaze/include/asm/config.h +++ b/arch/microblaze/include/asm/config.h @@ -12,6 +12,5 @@ #endif #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_GENERIC_BOARD #endif diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 4dc88f4d51..52e28f2ca5 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -43,8 +43,6 @@ PLATFORM_CPPFLAGS += $(cpuflags-y) PLATFORM_CPPFLAGS += -D__MIPS__ -__HAVE_ARCH_GENERIC_BOARD := y - # # From Linux arch/mips/Makefile # diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 34db79dd5c..0d96c52cd5 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -13,7 +13,6 @@ #include <config.h> #include <common.h> #include <asm/macro.h> -#include <version.h> /* * Jump vector table for EVIC mode diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 9b7c56dc85..82bd887961 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -17,5 +17,3 @@ PLATFORM_CPPFLAGS += -G0 LDFLAGS_FINAL += --gc-sections PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections - -__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/nios2/include/asm/config.h b/arch/nios2/include/asm/config.h index 476a32bdc6..9c13848ea2 100644 --- a/arch/nios2/include/asm/config.h +++ b/arch/nios2/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_GLOBAL_DATA #endif diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index fec02f2b82..83b49b58c5 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -12,13 +12,11 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections LDFLAGS_FINAL += --bss-plt -PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \ - -meabi -PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -PLATFORM_LDFLAGS += -n +PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \ +-fdata-sections -mcall-linux -# Support generic board on PPC -__HAVE_ARCH_GENERIC_BOARD := y +PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32 +PLATFORM_LDFLAGS += -m32 -melf32ppclinux # # When cross-compiling on NetBSD, we have to define __PPC__ or else we diff --git a/arch/powerpc/cpu/mpc8260/kgdb.S b/arch/powerpc/cpu/mpc8260/kgdb.S index 1432344bcc..bc9c62852c 100644 --- a/arch/powerpc/cpu/mpc8260/kgdb.S +++ b/arch/powerpc/cpu/mpc8260/kgdb.S @@ -7,7 +7,6 @@ #include <config.h> #include <command.h> #include <mpc8260.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index a2c0ad4244..0e0daf5a44 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -8,7 +8,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc85xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc86xx/cache.S b/arch/powerpc/cpu/mpc86xx/cache.S index 0bb058b043..536d9b9d73 100644 --- a/arch/powerpc/cpu/mpc86xx/cache.S +++ b/arch/powerpc/cpu/mpc86xx/cache.S @@ -1,6 +1,5 @@ #include <config.h> #include <mpc86xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc86xx/release.S b/arch/powerpc/cpu/mpc86xx/release.S index 461f6ec7df..3977049dc3 100644 --- a/arch/powerpc/cpu/mpc86xx/release.S +++ b/arch/powerpc/cpu/mpc86xx/release.S @@ -6,7 +6,6 @@ */ #include <config.h> #include <mpc86xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/mpc8xx/kgdb.S b/arch/powerpc/cpu/mpc8xx/kgdb.S index e774d1e70a..0ea1a06c7a 100644 --- a/arch/powerpc/cpu/mpc8xx/kgdb.S +++ b/arch/powerpc/cpu/mpc8xx/kgdb.S @@ -7,7 +7,6 @@ #include <config.h> #include <command.h> #include <mpc8xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index f274c5d564..31abd69896 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -7,7 +7,6 @@ #include <config.h> #include <command.h> #include <asm/ppc4xx.h> -#include <version.h> #define CONFIG_405GP 1 /* needed for Linux kernel header files */ diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 7b84f02a0a..b05a90fb18 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE -PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD +PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM PLATFORM_LIBS += -lrt # Define this to avoid linking with SDL, which requires SDL libraries @@ -16,9 +16,6 @@ PLATFORM_CPPFLAGS += $(shell sdl-config --cflags) endif endif -# Support generic board on sandbox -__HAVE_ARCH_GENERIC_BOARD := y - cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \ -Wl,--start-group $(u-boot-main) -Wl,--end-group \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S index 5b92a01571..ebf731a3ab 100644 --- a/arch/sh/cpu/sh2/start.S +++ b/arch/sh/cpu/sh2/start.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> .text .align 2 diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S index c26a0b6a2c..7a934e24d4 100644 --- a/arch/sh/cpu/sh3/start.S +++ b/arch/sh/cpu/sh3/start.S @@ -10,7 +10,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> .text .align 2 diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S index 238aa43662..21644b5e67 100644 --- a/arch/sh/cpu/sh4/start.S +++ b/arch/sh/cpu/sh4/start.S @@ -7,7 +7,6 @@ #include <asm-offsets.h> #include <config.h> -#include <version.h> .text .align 2 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 35d24e4aca..da271158f1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -76,9 +76,6 @@ config DM_GPIO config DM_SERIAL default y -config SYS_MALLOC_F - default y - config SYS_MALLOC_F_LEN default 0x800 diff --git a/arch/x86/config.mk b/arch/x86/config.mk index bb2da4637e..999143e9df 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -17,9 +17,6 @@ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm PLATFORM_CPPFLAGS += -march=i386 -m32 -# Support generic board on x86 -__HAVE_ARCH_GENERIC_BOARD := y - PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -m elf_i386 diff --git a/arch/x86/cpu/quark/hte.c b/arch/x86/cpu/quark/hte.c index 372815d8c1..db601e4efb 100644 --- a/arch/x86/cpu/quark/hte.c +++ b/arch/x86/cpu/quark/hte.c @@ -20,9 +20,9 @@ */ static void hte_enable_all_errors(void) { - msg_port_write(HTE, 0x000200A2, 0xFFFFFFFF); - msg_port_write(HTE, 0x000200A3, 0x000000FF); - msg_port_write(HTE, 0x000200A4, 0x00000000); + msg_port_write(HTE, 0x000200a2, 0xffffffff); + msg_port_write(HTE, 0x000200a3, 0x000000ff); + msg_port_write(HTE, 0x000200a4, 0x00000000); } /** @@ -32,7 +32,7 @@ static void hte_enable_all_errors(void) */ static u32 hte_check_errors(void) { - return msg_port_read(HTE, 0x000200A7); + return msg_port_read(HTE, 0x000200a7); } /** @@ -44,11 +44,11 @@ static void hte_wait_for_complete(void) ENTERFN(); - do {} while ((msg_port_read(HTE, 0x00020012) & BIT30) != 0); + do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0); tmp = msg_port_read(HTE, 0x00020011); - tmp |= BIT9; - tmp &= ~(BIT12 | BIT13); + tmp |= (1 << 9); + tmp &= ~((1 << 12) | (1 << 13)); msg_port_write(HTE, 0x00020011, tmp); LEAVEFN(); @@ -65,9 +65,9 @@ static void hte_clear_error_regs(void) * Clear all HTE errors and enable error checking * for burst and chunk. */ - tmp = msg_port_read(HTE, 0x000200A1); - tmp |= BIT8; - msg_port_write(HTE, 0x000200A1, tmp); + tmp = msg_port_read(HTE, 0x000200a1); + tmp |= (1 << 8); + msg_port_write(HTE, 0x000200a1, tmp); } /** @@ -91,25 +91,25 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr, u32 offset; if (first_run) { - msg_port_write(HTE, 0x00020020, 0x01B10021); + msg_port_write(HTE, 0x00020020, 0x01b10021); msg_port_write(HTE, 0x00020021, 0x06000000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020062, 0x00800015); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020061, 0x00030008); if (mode == WRITE_TRAIN) - pattern = 0xC33C0000; + pattern = 0xc33c0000; else /* READ_TRAIN */ - pattern = 0xAA5555AA; + pattern = 0xaa5555aa; - for (offset = 0x80; offset <= 0x8F; offset++) + for (offset = 0x80; offset <= 0x8f; offset++) msg_port_write(HTE, offset, pattern); } - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); msg_port_write(HTE, 0x00020011, 0x00011000); msg_port_write(HTE, 0x00020011, 0x00011100); @@ -119,7 +119,7 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr, * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for * any bytelane errors. */ - return (hte_check_errors() >> 8) & 0xFF; + return (hte_check_errors() >> 8) & 0xff; } /** @@ -153,7 +153,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, msg_port_write(HTE, 0x00020024, 0x06070000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020025, addr >> 6); - msg_port_write(HTE, 0x00020062, 0x0000002A); + msg_port_write(HTE, 0x00020062, 0x0000002a); msg_port_write(HTE, 0x00020063, seed_victim); msg_port_write(HTE, 0x00020064, seed_aggressor); msg_port_write(HTE, 0x00020065, seed_victim); @@ -163,21 +163,21 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, * * Start with bit0 */ - for (offset = 0x80; offset <= 0x8F; offset++) { + for (offset = 0x80; offset <= 0x8f; offset++) { if ((offset % 8) == victim_bit) msg_port_write(HTE, offset, 0x55555555); else - msg_port_write(HTE, offset, 0xCCCCCCCC); + msg_port_write(HTE, offset, 0xcccccccc); } msg_port_write(HTE, 0x00020061, 0x00000000); msg_port_write(HTE, 0x00020066, 0x03440000); - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); } tmp = 0x10001000 | (loop_cnt << 16); msg_port_write(HTE, 0x00020011, tmp); - msg_port_write(HTE, 0x00020011, tmp | BIT8); + msg_port_write(HTE, 0x00020011, tmp | (1 << 8)); hte_wait_for_complete(); @@ -185,7 +185,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for * any bytelane errors. */ - return (hte_check_errors() >> 8) & 0xFF; + return (hte_check_errors() >> 8) & 0xff; } /** @@ -219,14 +219,14 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag) msg_port_write(HTE, 0x00020062, 0x00000015); - for (offset = 0x80; offset <= 0x8F; offset++) - msg_port_write(HTE, offset, ((offset & 1) ? 0xA55A : 0x5AA5)); + for (offset = 0x80; offset <= 0x8f; offset++) + msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5)); msg_port_write(HTE, 0x00020021, 0x00000000); msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020066, 0x03000000); switch (flag) { @@ -243,7 +243,7 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag) break; default: DPF(D_INFO, "Unknown parameter for flag: %d\n", flag); - return 0xFFFFFFFF; + return 0xffffffff; } DPF(D_INFO, "hte_mem_init"); @@ -379,16 +379,16 @@ void hte_mem_op(u32 addr, u8 first_run, u8 is_write) msg_port_write(HTE, 0x00020021, 0x06000000); msg_port_write(HTE, 0x00020022, addr >> 6); msg_port_write(HTE, 0x00020062, 0x00800015); - msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); - msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); - msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); + msg_port_write(HTE, 0x00020063, 0xaaaaaaaa); + msg_port_write(HTE, 0x00020064, 0xcccccccc); + msg_port_write(HTE, 0x00020065, 0xf0f0f0f0); msg_port_write(HTE, 0x00020061, 0x00030008); - for (offset = 0x80; offset <= 0x8F; offset++) - msg_port_write(HTE, offset, 0xC33C0000); + for (offset = 0x80; offset <= 0x8f; offset++) + msg_port_write(HTE, offset, 0xc33c0000); } - msg_port_write(HTE, 0x000200A1, 0xFFFF1000); + msg_port_write(HTE, 0x000200a1, 0xffff1000); msg_port_write(HTE, 0x00020011, 0x00011000); msg_port_write(HTE, 0x00020011, 0x00011100); diff --git a/arch/x86/cpu/quark/hte.h b/arch/x86/cpu/quark/hte.h index 6577796fd6..e98c7ef41d 100644 --- a/arch/x86/cpu/quark/hte.h +++ b/arch/x86/cpu/quark/hte.h @@ -29,10 +29,10 @@ enum { #define HTE_LOOP_CNT 5 /* random seed for victim */ -#define HTE_LFSR_VICTIM_SEED 0xF294BA21 +#define HTE_LFSR_VICTIM_SEED 0xf294ba21 /* random seed for aggressor */ -#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D +#define HTE_LFSR_AGRESSOR_SEED 0xeba7492d u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag); u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr, diff --git a/arch/x86/cpu/quark/mrc.c b/arch/x86/cpu/quark/mrc.c index 7eb34c5302..6e774cbcd8 100644 --- a/arch/x86/cpu/quark/mrc.c +++ b/arch/x86/cpu/quark/mrc.c @@ -34,6 +34,7 @@ */ #include <common.h> +#include <version.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> #include "mrc_util.h" @@ -105,8 +106,8 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * Column: 11 for 8Gbx8, else 10 */ mrc_params->column_bits[0] = - ((dram_params[0].density == 4) && - (dram_width == X8)) ? (11) : (10); + (dram_params[0].density == 4) && + (dram_width == X8) ? 11 : 10; /* * Determine row bits: @@ -117,9 +118,9 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * 4Gbx16=15 4Gbx8=16 * 8Gbx16=16 8Gbx8=16 */ - mrc_params->row_bits[0] = 12 + (dram_params[0].density) + - (((dram_params[0].density < 4) && - (dram_width == X8)) ? (1) : (0)); + mrc_params->row_bits[0] = 12 + dram_params[0].density + + (dram_params[0].density < 4) && + (dram_width == X8) ? 1 : 0; /* * Determine per-channel memory size: @@ -137,7 +138,7 @@ static void mrc_adjust_params(struct mrc_params *mrc_params) * 4Gb x16 0x040000000 (1024MB) * 4Gb x8 0x080000000 (2048MB) */ - mrc_params->channel_size[0] = (1 << dram_params[0].density); + mrc_params->channel_size[0] = 1 << dram_params[0].density; mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1; mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1; mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2; @@ -192,7 +193,7 @@ void mrc_init(struct mrc_params *mrc_params) ENTERFN(); DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION, - __DATE__, __TIME__); + U_BOOT_DATE, U_BOOT_TIME); /* Set up the data structures used by mrc_mem_init() */ mrc_adjust_params(mrc_params); diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 3a79ae551b..49d803d794 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -18,14 +18,14 @@ static const uint8_t vref_codes[64] = { /* lowest to highest */ - 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38, + 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, - 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28, + 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f }; void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask) @@ -80,7 +80,7 @@ void select_mem_mgr(void) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT28; + dco &= ~DCO_PMICTL; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -94,7 +94,7 @@ void select_hte(void) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco |= BIT28; + dco |= DCO_PMICTL; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -151,26 +151,25 @@ void set_rcvn(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) : - (BIT11 | BIT10 | BIT9 | BIT8); - temp = (byte_lane & BIT0) ? ((pi_count / HALF_CLK) << 20) : - ((pi_count / HALF_CLK) << 8); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf00000 : 0xf00; + temp = (byte_lane & 1) ? (pi_count / HALF_CLK) << 20 : + (pi_count / HALF_CLK) << 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f000000; temp = pi_count << 24; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -179,25 +178,25 @@ void set_rcvn(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[08/11] (+1 select) * BL0/1 -> B01DBCTL1[02/05] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT5 : BIT2; + msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT11 : BIT8; + msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe0); } @@ -224,11 +223,11 @@ uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[11:08] (0x0-0xF) * BL1 -> B01PTRCTL0[23:20] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? 20 : 8; - temp &= 0xF; + temp >>= (byte_lane & 1) ? 20 : 8; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -238,12 +237,12 @@ uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F) * BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -275,10 +274,10 @@ void set_rdqs(uint8_t channel, uint8_t rank, * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) */ - reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x7f; temp = pi_count << 0; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -310,13 +309,13 @@ uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47) * BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47) */ - reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); /* Adjust PI_COUNT */ - pi_count = temp & 0x7F; + pi_count = temp & 0x7f; LEAVEFN(); @@ -346,26 +345,25 @@ void set_wdqs(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT19 | BIT18 | BIT17 | BIT16) : - (BIT7 | BIT6 | BIT5 | BIT4); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf0000 : 0xf0; temp = pi_count / HALF_CLK; - temp <<= (byte_lane & BIT0) ? 16 : 4; + temp <<= (byte_lane & 1) ? 16 : 4; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f0000; temp = pi_count << 16; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -374,25 +372,25 @@ void set_wdqs(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[07/10] (+1 select) * BL0/1 -> B01DBCTL1[01/04] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT4 : BIT1; + msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT10 : BIT7; + msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe2); } @@ -419,11 +417,11 @@ uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[07:04] (0x0-0xF) * BL1 -> B01PTRCTL0[19:16] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? 16 : 4; - temp &= 0xF; + temp >>= (byte_lane & 1) ? 16 : 4; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = (temp * HALF_CLK); @@ -433,12 +431,12 @@ uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F) * BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 16; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -471,26 +469,25 @@ void set_wdq(uint8_t channel, uint8_t rank, * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); - msk = (byte_lane & BIT0) ? (BIT15 | BIT14 | BIT13 | BIT12) : - (BIT3 | BIT2 | BIT1 | BIT0); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; + msk = (byte_lane & 1) ? 0xf000 : 0xf; temp = pi_count / HALF_CLK; - temp <<= (byte_lane & BIT0) ? 12 : 0; + temp <<= (byte_lane & 1) ? 12 : 0; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); - msk = (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); + msk = 0x3f00; temp = pi_count << 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -499,25 +496,25 @@ void set_wdq(uint8_t channel, uint8_t rank, * BL0/1 -> B01DBCTL1[06/09] (+1 select) * BL0/1 -> B01DBCTL1[00/03] (enable) */ - reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (byte_lane & BIT0) ? BIT3 : BIT0; + msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (byte_lane & BIT0) ? BIT9 : BIT6; + msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) { + if (pi_count > 0x3f) { training_message(channel, rank, byte_lane); mrc_post_code(0xee, 0xe3); } @@ -544,11 +541,11 @@ uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B01PTRCTL0[03:00] (0x0-0xF) * BL1 -> B01PTRCTL0[15:12] (0x0-0xF) */ - reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET); + reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); - temp >>= (byte_lane & BIT0) ? (12) : (0); - temp &= 0xF; + temp >>= (byte_lane & 1) ? 12 : 0; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -558,12 +555,12 @@ uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane) * BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F) * BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F) */ - reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0; - reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)); + reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0; + reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= 8; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -589,14 +586,14 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * RDPTR (1/2 MCLK, 64 PIs) * CMDPTRREG[11:08] (0x0-0xF) */ - reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT11 | BIT10 | BIT9 | BIT8); + reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xf00; temp = pi_count / HALF_CLK; temp <<= 8; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) @@ -609,18 +606,13 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) */ - reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); - - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); - + reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; + msk = 0x3f3f3f3f; temp = (pi_count << 24) | (pi_count << 16) | (pi_count << 8) | (pi_count << 0); mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = CMDDLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); /* PO */ + reg = CMDDLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; /* PO */ mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* @@ -628,24 +620,24 @@ void set_wcmd(uint8_t channel, uint32_t pi_count) * CMDCFGREG0[17] (+1 select) * CMDCFGREG0[16] (enable) */ - reg = CMDCFGREG0 + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDCFGREG0 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= BIT16; + msk |= (1 << 16); if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= BIT17; + msk |= (1 << 17); if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe4); LEAVEFN(); @@ -667,10 +659,10 @@ uint32_t get_wcmd(uint8_t channel) * RDPTR (1/2 MCLK, 64 PIs) * CMDPTRREG[11:08] (0x0-0xF) */ - reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 8; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -686,10 +678,10 @@ uint32_t get_wcmd(uint8_t channel) * CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused) * CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused) */ - reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 16; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -716,13 +708,13 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCPTRREG[15:12] -> CLK1 (0x0-0xF) * CCPTRREG[11:08] -> CLK0 (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xff00; temp = ((pi_count / HALF_CLK) << 12) | ((pi_count / HALF_CLK) << 8); mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) @@ -731,16 +723,18 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) */ reg = rank ? ECCB1DLLPICODER0 : ECCB1DLLPICODER0; reg += (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8); + msk = 0x3f3f00; temp = (pi_count << 16) | (pi_count << 8); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER1 : ECCB1DLLPICODER1; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER2 : ECCB1DLLPICODER2; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); + reg = rank ? ECCB1DLLPICODER3 : ECCB1DLLPICODER3; reg += (channel * DDRIOCCC_CH_OFFSET); mrc_alt_write_mask(DDRPHY, reg, temp, msk); @@ -750,24 +744,24 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCCFGREG1[11:08] (+1 select) * CCCFGREG1[03:00] (enable) */ - reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (BIT3 | BIT2 | BIT1 | BIT0); + msk |= 0xf; if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (BIT11 | BIT10 | BIT9 | BIT8); + msk |= 0xf00; if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe5); LEAVEFN(); @@ -790,10 +784,10 @@ uint32_t get_wclk(uint8_t channel, uint8_t rank) * CCPTRREG[15:12] -> CLK1 (0x0-0xF) * CCPTRREG[11:08] -> CLK0 (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= rank ? 12 : 8; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -807,7 +801,7 @@ uint32_t get_wclk(uint8_t channel, uint8_t rank) reg += (channel * DDRIOCCC_CH_OFFSET); temp = msg_port_alt_read(DDRPHY, reg); temp >>= rank ? 16 : 8; - temp &= 0x3F; + temp &= 0x3f; pi_count += temp; @@ -835,28 +829,31 @@ void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCPTRREG[31:28] (0x0-0xF) * CCPTRREG[27:24] (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; + msk = 0xff000000; temp = ((pi_count / HALF_CLK) << 28) | ((pi_count / HALF_CLK) << 24); mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* Adjust PI_COUNT */ - pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK; + pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK; /* * PI (1/64 MCLK, 1 PIs) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) */ - reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); - msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24); + reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; + msk = 0x3f000000; temp = (pi_count << 24); mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER1 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER2 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER2 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); - reg = ECCB1DLLPICODER3 + (channel * DDRIOCCC_CH_OFFSET); + + reg = ECCB1DLLPICODER3 + channel * DDRIOCCC_CH_OFFSET; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* @@ -864,24 +861,24 @@ void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count) * CCCFGREG1[13:12] (+1 select) * CCCFGREG1[05:04] (enable) */ - reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET); + reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET; msk = 0x00; temp = 0x00; /* enable */ - msk |= (BIT5 | BIT4); + msk |= 0x30; if ((pi_count < EARLY_DB) || (pi_count > LATE_DB)) temp |= msk; /* select */ - msk |= (BIT13 | BIT12); + msk |= 0x3000; if (pi_count < EARLY_DB) temp |= msk; mrc_alt_write_mask(DDRPHY, reg, temp, msk); /* error check */ - if (pi_count > 0x3F) + if (pi_count > 0x3f) mrc_post_code(0xee, 0xe6); LEAVEFN(); @@ -906,10 +903,10 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) * CCPTRREG[31:28] (0x0-0xF) * CCPTRREG[27:24] (0x0-0xF) */ - reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); + reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0xF; + temp &= 0xf; /* Adjust PI_COUNT */ pi_count = temp * HALF_CLK; @@ -919,10 +916,10 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) * ECCB1DLLPICODER?[29:24] (0x00-0x3F) */ - reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); + reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; temp = msg_port_alt_read(DDRPHY, reg); temp >>= 24; - temp &= 0x3F; + temp &= 0x3f; /* Adjust PI_COUNT */ pi_count += temp; @@ -938,17 +935,16 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank) */ void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting) { - uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL); + uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL; ENTERFN(); DPF(D_TRN, "Vref ch%d ln%d : val=%03X\n", channel, byte_lane, setting); - mrc_alt_write_mask(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) + - ((byte_lane >> 1) * DDRIODQ_BL_OFFSET)), - (vref_codes[setting] << 2), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + mrc_alt_write_mask(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET + + (byte_lane >> 1) * DDRIODQ_BL_OFFSET, + vref_codes[setting] << 2, 0xfc); /* * need to wait ~300ns for Vref to settle @@ -969,15 +965,15 @@ uint32_t get_vref(uint8_t channel, uint8_t byte_lane) { uint8_t j; uint32_t ret_val = sizeof(vref_codes) / 2; - uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL); + uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL; uint32_t temp; ENTERFN(); - temp = msg_port_alt_read(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) + - ((byte_lane >> 1) * DDRIODQ_BL_OFFSET))); + temp = msg_port_alt_read(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET + + (byte_lane >> 1) * DDRIODQ_BL_OFFSET); temp >>= 2; - temp &= 0x3F; + temp &= 0x3f; for (j = 0; j < sizeof(vref_codes); j++) { if (vref_codes[j] == temp) { @@ -997,7 +993,7 @@ uint32_t get_vref(uint8_t channel, uint8_t byte_lane) */ uint32_t get_addr(uint8_t channel, uint8_t rank) { - uint32_t offset = 0x02000000; /* 32MB */ + uint32_t offset = 32 * 1024 * 1024; /* 32MB */ /* Begin product specific code */ if (channel > 0) { @@ -1040,8 +1036,8 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, uint32_t address = get_addr(channel, rank); /* initialise msk[] */ - msk[0] = rcvn ? BIT1 : BIT9; /* BL0 */ - msk[1] = rcvn ? BIT0 : BIT8; /* BL1 */ + msk[0] = rcvn ? (1 << 1) : (1 << 9); /* BL0 */ + msk[1] = rcvn ? (1 << 0) : (1 << 8); /* BL1 */ /* cycle through each byte lane group */ for (bl_grp = 0; bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { @@ -1056,9 +1052,9 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, * DQTRAINSTS register */ sampled_val[j] = msg_port_alt_read(DDRPHY, - (DQTRAINSTS + - (bl_grp * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET))); + DQTRAINSTS + + bl_grp * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET); } /* @@ -1076,7 +1072,7 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, num_0s++; } if (num_1s > num_0s) - ret_val |= (1 << (bl + (bl_grp * 2))); + ret_val |= (1 << (bl + bl_grp * 2)); } } @@ -1116,10 +1112,10 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], /* increase sample delay by 26 PI (0.2 CLK) */ if (rcvn) { set_rcvn(channel, rank, bl, - delay[bl] + (sample * SAMPLE_DLY)); + delay[bl] + sample * SAMPLE_DLY); } else { set_wdqs(channel, rank, bl, - delay[bl] + (sample * SAMPLE_DLY)); + delay[bl] + sample * SAMPLE_DLY); } } @@ -1129,7 +1125,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], DPF(D_TRN, "Find rising edge %s ch%d rnk%d: #%d dly=%d dqs=%02X\n", - (rcvn ? "RCVN" : "WDQS"), channel, rank, sample, + rcvn ? "RCVN" : "WDQS", channel, rank, sample, sample * SAMPLE_DLY, sample_result[sample]); } @@ -1137,7 +1133,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], * This pattern will help determine where we landed and ultimately * how to place RCVEN/WDQS. */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* build transition_pattern (MSB is 1st sample) */ transition_pattern = 0; for (sample = 0; sample < SAMPLE_CNT; sample++) { @@ -1202,7 +1198,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], /* take a sample */ temp = sample_dqs(mrc_params, channel, rank, rcvn); /* check all each byte lane for proper edge */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (temp & (1 << bl)) { /* sampled "1" */ if (direction[bl] == BACKWARD) { @@ -1340,10 +1336,10 @@ void lfsr32(uint32_t *lfsr_ptr) lfsr = *lfsr_ptr; for (i = 0; i < 32; i++) { - bit = 1 ^ (lfsr & BIT0); - bit = bit ^ ((lfsr & BIT1) >> 1); - bit = bit ^ ((lfsr & BIT2) >> 2); - bit = bit ^ ((lfsr & BIT22) >> 22); + bit = 1 ^ (lfsr & 1); + bit = bit ^ ((lfsr & 2) >> 1); + bit = bit ^ ((lfsr & 4) >> 2); + bit = bit ^ ((lfsr & 0x400000) >> 22); lfsr = ((lfsr >> 1) | (bit << 31)); } @@ -1362,16 +1358,16 @@ void clear_pointers(void) for (channel = 0; channel < NUM_CHANNELS; channel++) { for (bl = 0; bl < NUM_BYTE_LANES; bl++) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (channel * DDRIODQ_CH_OFFSET) + - ((bl >> 1) * DDRIODQ_BL_OFFSET)), - ~BIT8, BIT8); + B01PTRCTL1 + + channel * DDRIODQ_CH_OFFSET + + (bl >> 1) * DDRIODQ_BL_OFFSET, + ~(1 << 8), (1 << 8)); mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (channel * DDRIODQ_CH_OFFSET) + - ((bl >> 1) * DDRIODQ_BL_OFFSET)), - BIT8, BIT8); + B01PTRCTL1 + + channel * DDRIODQ_CH_OFFSET + + (bl >> 1) * DDRIODQ_BL_OFFSET, + (1 << 8), (1 << 8)); } } @@ -1412,7 +1408,7 @@ static void print_timings_internal(uint8_t algo, uint8_t channel, uint8_t rank, break; } - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { switch (algo) { case RCVN: DPF(D_INFO, " %03d", get_rcvn(channel, rank, bl)); diff --git a/arch/x86/cpu/quark/mrc_util.h b/arch/x86/cpu/quark/mrc_util.h index f0ddbce3c5..a63d1f91e9 100644 --- a/arch/x86/cpu/quark/mrc_util.h +++ b/arch/x86/cpu/quark/mrc_util.h @@ -41,40 +41,6 @@ #define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__) #define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__) -/* Generic Register Bits */ -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - /* Message Bus Port */ #define MEM_CTLR 0x01 #define HOST_BRIDGE 0x03 diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index dccf7ac5f5..25edcf71cb 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -6,6 +6,8 @@ #include <common.h> #include <mmc.h> +#include <netdev.h> +#include <phy.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/post.h> @@ -116,3 +118,20 @@ int cpu_mmc_init(bd_t *bis) return pci_mmc_init("Quark SDHCI", mmc_supported, ARRAY_SIZE(mmc_supported)); } + +int cpu_eth_init(bd_t *bis) +{ + u32 base; + int ret0, ret1; + + pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base); + ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); + + pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base); + ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII); + + if (ret0 < 0 && ret1 < 0) + return -1; + else + return 0; +} diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index e34bec4c80..3ffe92b67b 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -60,7 +60,7 @@ void clear_self_refresh(struct mrc_params *mrc_params) ENTERFN(); /* clear the PMSTS Channel Self Refresh bits */ - mrc_write_mask(MEM_CTLR, PMSTS, BIT0, BIT0); + mrc_write_mask(MEM_CTLR, PMSTS, PMSTS_DISR, PMSTS_DISR); LEAVEFN(); } @@ -101,47 +101,47 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) wl = 5 + mrc_params->ddr_speed; - dtr0 &= ~(BIT0 | BIT1); + dtr0 &= ~DTR0_DFREQ_MASK; dtr0 |= mrc_params->ddr_speed; - dtr0 &= ~(BIT12 | BIT13 | BIT14); + dtr0 &= ~DTR0_TCL_MASK; tmp1 = tcl - 5; dtr0 |= ((tcl - 5) << 12); - dtr0 &= ~(BIT4 | BIT5 | BIT6 | BIT7); + dtr0 &= ~DTR0_TRP_MASK; dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */ - dtr0 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr0 &= ~DTR0_TRCD_MASK; dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */ - dtr1 &= ~(BIT0 | BIT1 | BIT2); + dtr1 &= ~DTR1_TWCL_MASK; tmp2 = wl - 3; dtr1 |= (wl - 3); - dtr1 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr1 &= ~DTR1_TWTP_MASK; dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */ - dtr1 &= ~(BIT28 | BIT29 | BIT30); + dtr1 &= ~DTR1_TRTP_MASK; dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */ - dtr1 &= ~(BIT24 | BIT25); + dtr1 &= ~DTR1_TRRD_MASK; dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ - dtr1 &= ~(BIT4 | BIT5); + dtr1 &= ~DTR1_TCMD_MASK; dtr1 |= (1 << 4); - dtr1 &= ~(BIT20 | BIT21 | BIT22 | BIT23); + dtr1 &= ~DTR1_TRAS_MASK; dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */ - dtr1 &= ~(BIT16 | BIT17 | BIT18 | BIT19); + dtr1 &= ~DTR1_TFAW_MASK; dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ /* Set 4 Clock CAS to CAS delay (multi-burst) */ - dtr1 &= ~(BIT12 | BIT13); + dtr1 &= ~DTR1_TCCD_MASK; - dtr2 &= ~(BIT0 | BIT1 | BIT2); + dtr2 &= ~DTR2_TRRDR_MASK; dtr2 |= 1; - dtr2 &= ~(BIT8 | BIT9 | BIT10); + dtr2 &= ~DTR2_TWWDR_MASK; dtr2 |= (2 << 8); - dtr2 &= ~(BIT16 | BIT17 | BIT18 | BIT19); + dtr2 &= ~DTR2_TRWDR_MASK; dtr2 |= (2 << 16); - dtr3 &= ~(BIT0 | BIT1 | BIT2); + dtr3 &= ~DTR3_TWRDR_MASK; dtr3 |= 2; - dtr3 &= ~(BIT4 | BIT5 | BIT6); + dtr3 &= ~DTR3_TXXXX_MASK; dtr3 |= (2 << 4); - dtr3 &= ~(BIT8 | BIT9 | BIT10 | BIT11); + dtr3 &= ~DTR3_TRWSR_MASK; if (mrc_params->ddr_speed == DDRFREQ_800) { /* Extended RW delay (+1) */ dtr3 |= ((tcl - 5 + 1) << 8); @@ -150,24 +150,24 @@ void prog_ddr_timing_control(struct mrc_params *mrc_params) dtr3 |= ((tcl - 5 + 1) << 8); } - dtr3 &= ~(BIT13 | BIT14 | BIT15 | BIT16); + dtr3 &= ~DTR3_TWRSR_MASK; dtr3 |= ((4 + wl + twtr - 11) << 13); - dtr3 &= ~(BIT22 | BIT23); + dtr3 &= ~DTR3_TXP_MASK; if (mrc_params->ddr_speed == DDRFREQ_800) dtr3 |= ((MMAX(0, 1 - 1)) << 22); else dtr3 |= ((MMAX(0, 2 - 1)) << 22); - dtr4 &= ~(BIT0 | BIT1); + dtr4 &= ~DTR4_WRODTSTRT_MASK; dtr4 |= 1; - dtr4 &= ~(BIT4 | BIT5 | BIT6); + dtr4 &= ~DTR4_WRODTSTOP_MASK; dtr4 |= (1 << 4); - dtr4 &= ~(BIT8 | BIT9 | BIT10); + dtr4 &= ~DTR4_XXXX1_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); - dtr4 &= ~(BIT12 | BIT13 | BIT14); + dtr4 &= ~DTR4_XXXX2_MASK; dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12); - dtr4 &= ~(BIT15 | BIT16); + dtr4 &= ~(DTR4_ODTDIS | DTR4_TRGSTRDIS); msg_port_write(MEM_CTLR, DTR0, dtr0); msg_port_write(MEM_CTLR, DTR1, dtr1); @@ -191,25 +191,25 @@ void prog_decode_before_jedec(struct mrc_params *mrc_params) /* Disable power saving features */ dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 |= (BIT24 | BIT25); - dpmc0 &= ~(BIT16 | BIT17 | BIT18); - dpmc0 &= ~BIT23; + dpmc0 |= (DPMC0_CLKGTDIS | DPMC0_DISPWRDN); + dpmc0 &= ~DPMC0_PCLSTO_MASK; + dpmc0 &= ~DPMC0_DYNSREN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); /* Disable out of order transactions */ dsch = msg_port_read(MEM_CTLR, DSCH); - dsch |= (BIT8 | BIT12); + dsch |= (DSCH_OOODIS | DSCH_NEWBYPDIS); msg_port_write(MEM_CTLR, DSCH, dsch); /* Disable issuing the REF command */ drfc = msg_port_read(MEM_CTLR, DRFC); - drfc &= ~(BIT12 | BIT13 | BIT14); + drfc &= ~DRFC_TREFI_MASK; msg_port_write(MEM_CTLR, DRFC, drfc); /* Disable ZQ calibration short */ dcal = msg_port_read(MEM_CTLR, DCAL); - dcal &= ~(BIT8 | BIT9 | BIT10); - dcal &= ~(BIT12 | BIT13); + dcal &= ~DCAL_ZQCINT_MASK; + dcal &= ~DCAL_SRXZQCL_MASK; msg_port_write(MEM_CTLR, DCAL, dcal); /* @@ -218,9 +218,9 @@ void prog_decode_before_jedec(struct mrc_params *mrc_params) */ drp = 0; if (mrc_params->rank_enables & 1) - drp |= BIT0; + drp |= DRP_RKEN0; if (mrc_params->rank_enables & 2) - drp |= BIT1; + drp |= DRP_RKEN1; msg_port_write(MEM_CTLR, DRP, drp); LEAVEFN(); @@ -238,14 +238,14 @@ void perform_ddr_reset(struct mrc_params *mrc_params) ENTERFN(); /* Set COLDWAKE bit before sending the WAKE message */ - mrc_write_mask(MEM_CTLR, DRMC, BIT16, BIT16); + mrc_write_mask(MEM_CTLR, DRMC, DRMC_COLDWAKE, DRMC_COLDWAKE); /* Send wake command to DUNIT (MUST be done before JEDEC) */ dram_wake_command(); /* Set default value */ msg_port_write(MEM_CTLR, DRMC, - (mrc_params->rd_odt_value == 0 ? BIT12 : 0)); + mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0); LEAVEFN(); } @@ -263,7 +263,7 @@ void ddrphy_init(struct mrc_params *mrc_params) uint8_t bl_grp; /* byte lane group counter (2 BLs per module) */ uint8_t bl_divisor = 1; /* byte lane divisor */ /* For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333 */ - uint8_t speed = mrc_params->ddr_speed & (BIT1 | BIT0); + uint8_t speed = mrc_params->ddr_speed & 3; uint8_t cas; uint8_t cwl; @@ -286,21 +286,21 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* Deassert DDRPHY Initialization Complete */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT20, BIT20); /* SPID_INIT_COMPLETE=0 */ + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 20), 1 << 20); /* SPID_INIT_COMPLETE=0 */ /* Deassert IOBUFACT */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT2, BIT2); /* IOBUFACTRST_N=0 */ + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 2), 1 << 2); /* IOBUFACTRST_N=0 */ /* Disable WRPTR */ mrc_alt_write_mask(DDRPHY, - (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)), - ~BIT0, BIT0); /* WRPTRENABLE=0 */ + CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, + ~(1 << 0), 1 << 0); /* WRPTRENABLE=0 */ } } /* Put PHY in reset */ - mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, BIT0); + mrc_alt_write_mask(DDRPHY, MASTERRSTN, 0, 1); /* Initialize DQ01, DQ23, CMD, CLK-CTL, COMP modules */ @@ -310,14 +310,14 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { /* Analog MUX select - IO2xCLKSEL */ mrc_alt_write_mask(DDRPHY, - (DQOBSCKEBBCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((bl_grp) ? (0x00) : (BIT22)), (BIT22)); + DQOBSCKEBBCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + bl_grp ? 0 : (1 << 22), 1 << 22); /* ODT Strength */ switch (mrc_params->rd_odt_value) { @@ -337,20 +337,20 @@ void ddrphy_init(struct mrc_params *mrc_params) /* ODT strength */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (temp << 5), (BIT6 | BIT5)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp << 5, 0x60); /* ODT strength */ mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (temp << 5), (BIT6 | BIT5)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp << 5, 0x60); /* Dynamic ODT/DIFFAMP */ - temp = (((cas) << 24) | ((cas) << 16) | - ((cas) << 8) | ((cas) << 0)); + temp = (cas << 24) | (cas << 16) | + (cas << 8) | (cas << 0); switch (speed) { case 0: temp -= 0x01010101; @@ -368,247 +368,199 @@ void ddrphy_init(struct mrc_params *mrc_params) /* Launch Time: ODT, DIFFAMP, ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B01LATCTL1 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + B01LATCTL1 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x1f1f1f1f); switch (speed) { /* HSD#234715 */ case 0: - temp = ((0x06 << 16) | (0x07 << 8)); + temp = (0x06 << 16) | (0x07 << 8); break; /* 800 */ case 1: - temp = ((0x07 << 16) | (0x08 << 8)); + temp = (0x07 << 16) | (0x08 << 8); break; /* 1066 */ case 2: - temp = ((0x09 << 16) | (0x0A << 8)); + temp = (0x09 << 16) | (0x0a << 8); break; /* 1333 */ case 3: - temp = ((0x0A << 16) | (0x0B << 8)); + temp = (0x0a << 16) | (0x0b << 8); break; /* 1600 */ } /* On Duration: ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B0ONDURCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8)); + B0ONDURCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003f3f00); /* On Duration: ODT, DIFFAMP */ mrc_alt_write_mask(DDRPHY, - (B1ONDURCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8)); + B1ONDURCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003f3f00); switch (mrc_params->rd_odt_value) { case 0: /* override DIFFAMP=on, ODT=off */ - temp = ((0x3F << 16) | (0x3f << 10)); + temp = (0x3f << 16) | (0x3f << 10); break; default: /* override DIFFAMP=on, ODT=on */ - temp = ((0x3F << 16) | (0x2A << 10)); + temp = (0x3f << 16) | (0x2a << 10); break; } /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | - BIT11 | BIT10)); + B0OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003ffc00); /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B1OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT15 | BIT14 | BIT13 | BIT12 | - BIT11 | BIT10)); + B1OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0x003ffc00); /* DLL Setup */ /* 1xCLK Domain Timings: tEDP,RCVEN,WDQS (PO) */ mrc_alt_write_mask(DDRPHY, - (B0LATCTL0 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (((cas + 7) << 16) | ((cas - 4) << 8) | - ((cwl - 2) << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT12 | BIT11 | BIT10 | BIT9 | - BIT8 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + B0LATCTL0 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + ((cas + 7) << 16) | ((cas - 4) << 8) | + ((cwl - 2) << 0), 0x003f1f1f); mrc_alt_write_mask(DDRPHY, - (B1LATCTL0 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (((cas + 7) << 16) | ((cas - 4) << 8) | - ((cwl - 2) << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT12 | BIT11 | BIT10 | BIT9 | - BIT8 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + B1LATCTL0 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + ((cas + 7) << 16) | ((cas - 4) << 8) | + ((cwl - 2) << 0), 0x003f1f1f); /* RCVEN Bypass (PO) */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x0 << 7) | (0x0 << 0)), - (BIT7 | BIT0)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x81); mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x0 << 7) | (0x0 << 0)), - (BIT7 | BIT0)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x81); /* TX */ mrc_alt_write_mask(DDRPHY, - (DQCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT16), (BIT16)); + DQCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 16, 1 << 16); mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT8), (BIT8)); + B01PTRCTL1 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 8, 1 << 8); /* RX (PO) */ /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ mrc_alt_write_mask(DDRPHY, - (B0VREFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + B0VREFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + (0x03 << 2) | (0x0 << 1) | (0x0 << 0), + 0xff); /* Internal Vref Code, Enable#, Ext_or_Int (1=Ext) */ mrc_alt_write_mask(DDRPHY, - (B1VREFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - ((0x03 << 2) | (0x0 << 1) | (0x0 << 0)), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + B1VREFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + (0x03 << 2) | (0x0 << 1) | (0x0 << 0), + 0xff); /* Per-Bit De-Skew Enable */ mrc_alt_write_mask(DDRPHY, - (B0RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (0), (BIT4)); + B0RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x10); /* Per-Bit De-Skew Enable */ mrc_alt_write_mask(DDRPHY, - (B1RXIOBUFCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (0), (BIT4)); + B1RXIOBUFCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 0x10); } /* CLKEBB */ mrc_alt_write_mask(DDRPHY, - (CMDOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)), - 0, (BIT23)); + CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, + 0, 1 << 23); /* Enable tristate control of cmd/address bus */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - 0, (BIT1 | BIT0)); + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 0, 0x03); /* ODT RCOMP */ mrc_alt_write_mask(DDRPHY, - (CMDRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)), - ((0x03 << 5) | (0x03 << 0)), - (BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET, + (0x03 << 5) | (0x03 << 0), 0x3ff); /* CMDPM* registers must be programmed in this order */ /* Turn On Delays: SFR (regulator), MPLL */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG4 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFFFU << 16) | (0xFFFF << 0)), - 0xFFFFFFFF); + CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* * Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, * VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT * for_PM_MSG_gt0, MDLL Turn On */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG3 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFU << 28) | (0xFFF << 16) | (0xF << 12) | - (0x616 << 0)), 0xFFFFFFFF); + CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET, + 0xfffff616, 0xffffffff); /* MPLL Divider Reset Delays */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG2 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Turn Off Delays: VREG, Staggered MDLL, MDLL, PI */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG1 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT */ mrc_alt_write_mask(DDRPHY, - (CMDPMDLYREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0xFFU << 24) | (0xFF << 16) | (0xFF << 8) | - (0xFF << 0)), 0xFFFFFFFF); + CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET, + 0xffffffff, 0xffffffff); /* Allow PUnit signals */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x6 << 8) | BIT6 | (0x4 << 0)), - (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | - BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT11 | - BIT10 | BIT9 | BIT8 | BIT6 | BIT3 | BIT2 | - BIT1 | BIT0)); + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + (0x6 << 8) | (0x1 << 6) | (0x4 << 0), + 0xffe00f4f); /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - ((0x3 << 4) | (0x7 << 0)), - (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + (0x3 << 4) | (0x7 << 0), 0x7f); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCOBSCKEBBCTL + (ch * DDRIOCCC_CH_OFFSET)), - 0, BIT24); /* CLKEBB */ + CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, + 0, 1 << 24); /* CLKEBB */ /* Buffer Enable: CS,CKE,ODT,CLK */ mrc_alt_write_mask(DDRPHY, - (CCCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x0 << 16) | (0x0 << 12) | (0x0 << 8) | - (0xF << 4) | BIT0), - (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT7 | BIT6 | BIT5 | BIT4 | BIT0)); + CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 0x1f, 0x000ffff1); /* ODT RCOMP */ mrc_alt_write_mask(DDRPHY, - (CCRCOMPODT + (ch * DDRIOCCC_CH_OFFSET)), - ((0x03 << 8) | (0x03 << 0)), - (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET, + (0x03 << 8) | (0x03 << 0), 0x00001f1f); /* DLL_VREG Bias Trim, VREF Tuning for DLL_VREG */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - ((0x3 << 4) | (0x7 << 0)), - (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | - BIT0)); + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + (0x3 << 4) | (0x7 << 0), 0x7f); /* * COMP (RON channel specific) @@ -618,66 +570,43 @@ void ddrphy_init(struct mrc_params *mrc_params) */ /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x08 << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x08 << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CMDVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0C << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0C << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0F << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0F << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x08 << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x08 << 24) | (0x03 << 16), 0x3f3f0000); /* RCOMP Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CTLVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0C << 24) | (0x03 << 16)), - (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | - BIT24 | BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16)); + CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0C << 24) | (0x03 << 16), 0x3f3f0000); /* DQS Swapped Input Enable */ mrc_alt_write_mask(DDRPHY, - (COMPEN1CH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT19 | BIT17), - (BIT31 | BIT30 | BIT19 | BIT17 | - BIT15 | BIT14)); + COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 19) | (1 << 17), 0xc00ac000); /* ODT VREF = 1.5 x 274/360+274 = 0.65V (code of ~50) */ /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x32 << 8) | (0x03 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x32 << 8) | (0x03 << 0), 0x00003f3f); /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (DQSVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x32 << 8) | (0x03 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x32 << 8) | (0x03 << 0), 0x00003f3f); /* ODT Vref PU/PD */ mrc_alt_write_mask(DDRPHY, - (CLKVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x0E << 8) | (0x05 << 0)), - (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x0E << 8) | (0x05 << 0), 0x00003f3f); /* * Slew rate settings are frequency specific, @@ -685,273 +614,227 @@ void ddrphy_init(struct mrc_params *mrc_params) * - DQ/DQS/DM/CLK SR: 4V/ns, * - CTRL/CMD SR: 1.5V/ns */ - temp = (0x0E << 16) | (0x0E << 12) | (0x08 << 8) | - (0x0B << 4) | (0x0B << 0); + temp = (0x0e << 16) | (0x0e << 12) | (0x08 << 8) | + (0x0b << 4) | (0x0b << 0); /* DCOMP Delay Select: CTL,CMD,CLK,DQS,DQ */ mrc_alt_write_mask(DDRPHY, - (DLYSELCH0 + (ch * DDRCOMP_CH_OFFSET)), - temp, - (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | - BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | - BIT3 | BIT2 | BIT1 | BIT0)); + DLYSELCH0 + ch * DDRCOMP_CH_OFFSET, + temp, 0x000fffff); /* TCO Vref CLK,DQS,DQ */ mrc_alt_write_mask(DDRPHY, - (TCOVREFCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x05 << 16) | (0x05 << 8) | (0x05 << 0)), - (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT5 | BIT4 | BIT3 | BIT2 | - BIT1 | BIT0)); + TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET, + (0x05 << 16) | (0x05 << 8) | (0x05 << 0), + 0x003f3f3f); /* ODTCOMP CMD/CTL PU/PD */ mrc_alt_write_mask(DDRPHY, - (CCBUFODTCH0 + (ch * DDRCOMP_CH_OFFSET)), - ((0x03 << 8) | (0x03 << 0)), - (BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | - BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); + CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET, + (0x03 << 8) | (0x03 << 0), + 0x00001f1f); /* COMP */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - 0, (BIT31 | BIT30 | BIT8)); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + 0, 0xc0000100); #ifdef BACKUP_COMPS /* DQ COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* DQS COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x10 << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x10 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* CLK COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0C << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0c << 16), + 0x801f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0C << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0c << 16), + 0x801f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x07 << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x07 << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x07 << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x07 << 16), + 0x801f0000); /* ODTCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKODTPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* ODTCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKODTPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0B << 16)), - (BIT31 | (0x0B << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0b << 16), + 0x801f0000); /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31), (BIT31)); + CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 31, 1 << 31); /* CMD COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CMDDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CMDDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CMDDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CMDDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* CTL COMP Overrides */ /* RCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CTLDRVPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* RCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CTLDRVPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0D << 16)), - (BIT31 | BIT21 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0d << 16), + 0x803f0000); /* DCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CTLDLYPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); /* DCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CTLDLYPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x0A << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x0a << 16), + 0x801f0000); #else /* DQ TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* DQS TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (DQSTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* CLK TCOCOMP Overrides */ /* TCOCOMP PU */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPUCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); /* TCOCOMP PD */ mrc_alt_write_mask(DDRPHY, - (CLKTCOPDCTLCH0 + (ch * DDRCOMP_CH_OFFSET)), - (BIT31 | (0x1F << 16)), - (BIT31 | BIT20 | BIT19 | - BIT18 | BIT17 | BIT16)); + CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, + (1 << 31) | (0x1f << 16), + 0x801f0000); #endif /* program STATIC delays */ @@ -962,7 +845,7 @@ void ddrphy_init(struct mrc_params *mrc_params) #endif for (rk = 0; rk < NUM_RANKS; rk++) { - if (mrc_params->rank_enables & (1<<rk)) { + if (mrc_params->rank_enables & (1 << rk)) { set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]); #ifdef BACKUP_WCTL set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]); @@ -976,86 +859,80 @@ void ddrphy_init(struct mrc_params *mrc_params) /* COMP (non channel specific) */ /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADRVPDCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADRVPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADRVPUCTL, 1 << 30, 1 << 30); /* RCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADRVPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADRVPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANAODTPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANAODTPDCTL, 1 << 30, 1 << 30); /* ODT: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANAODTPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANAODTPUCTL, 1 << 30, 1 << 30); /* ODT: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANAODTPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANAODTPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CMDANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CMDANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANADLYPDCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADLYPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADLYPUCTL, 1 << 30, 1 << 30); /* DCOMP: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CTLANADLYPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CTLANADLYPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQANATCOPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (CLKANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, CLKANATCOPDCTL, 1 << 30, 1 << 30); /* TCO: Dither PU Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANATCOPUCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANATCOPUCTL, 1 << 30, 1 << 30); /* TCO: Dither PD Enable */ - mrc_alt_write_mask(DDRPHY, (DQSANATCOPDCTL), (BIT30), (BIT30)); + mrc_alt_write_mask(DDRPHY, DQSANATCOPDCTL, 1 << 30, 1 << 30); /* TCOCOMP: Pulse Count */ - mrc_alt_write_mask(DDRPHY, (TCOCNTCTRL), (0x1 << 0), (BIT1 | BIT0)); + mrc_alt_write_mask(DDRPHY, TCOCNTCTRL, 1, 3); /* ODT: CMD/CTL PD/PU */ - mrc_alt_write_mask(DDRPHY, - (CHNLBUFSTATIC), ((0x03 << 24) | (0x03 << 16)), - (BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | - BIT20 | BIT19 | BIT18 | BIT17 | BIT16)); + mrc_alt_write_mask(DDRPHY, CHNLBUFSTATIC, + (0x03 << 24) | (0x03 << 16), 0x1f1f0000); /* Set 1us counter */ - mrc_alt_write_mask(DDRPHY, - (MSCNTR), (0x64 << 0), - (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)); - mrc_alt_write_mask(DDRPHY, - (LATCH1CTL), (0x1 << 28), - (BIT30 | BIT29 | BIT28)); + mrc_alt_write_mask(DDRPHY, MSCNTR, 0x64, 0xff); + mrc_alt_write_mask(DDRPHY, LATCH1CTL, 0x1 << 28, 0x70000000); /* Release PHY from reset */ - mrc_alt_write_mask(DDRPHY, MASTERRSTN, BIT0, BIT0); + mrc_alt_write_mask(DDRPHY, MASTERRSTN, 1, 1); /* STEP1 */ mrc_post_code(0x03, 0x11); @@ -1064,30 +941,30 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { mrc_alt_write_mask(DDRPHY, - (DQMDLLCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT13), - (BIT13)); /* Enable VREG */ + DQMDLLCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 13, + 1 << 13); /* Enable VREG */ delay_n(3); } /* ECC */ - mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL), - (BIT13), (BIT13)); /* Enable VREG */ + mrc_alt_write_mask(DDRPHY, ECCMDLLCTL, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); /* CMD */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT13), (BIT13)); /* Enable VREG */ + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT13), (BIT13)); /* Enable VREG */ + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 13, 1 << 13); /* Enable VREG */ delay_n(3); } } @@ -1100,30 +977,30 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { mrc_alt_write_mask(DDRPHY, - (DQMDLLCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT17), - (BIT17)); /* Enable MCDLL */ + DQMDLLCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 17, + 1 << 17); /* Enable MCDLL */ delay_n(50); } /* ECC */ - mrc_alt_write_mask(DDRPHY, (ECCMDLLCTL), - (BIT17), (BIT17)); /* Enable MCDLL */ + mrc_alt_write_mask(DDRPHY, ECCMDLLCTL, + 1 << 17, 1 << 17); /* Enable MCDLL */ delay_n(50); /* CMD */ mrc_alt_write_mask(DDRPHY, - (CMDMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT18), (BIT18)); /* Enable MCDLL */ + CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 18, 1 << 18); /* Enable MCDLL */ delay_n(50); /* CLK-CTL */ mrc_alt_write_mask(DDRPHY, - (CCMDLLCTL + (ch * DDRIOCCC_CH_OFFSET)), - (BIT18), (BIT18)); /* Enable MCDLL */ + CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, + 1 << 18, 1 << 18); /* Enable MCDLL */ delay_n(50); } } @@ -1136,54 +1013,47 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* DQ01-DQ23 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { #ifdef FORCE_16BIT_DDRIO - temp = ((bl_grp) && + temp = (bl_grp && (mrc_params->channel_width == X16)) ? - ((0x1 << 12) | (0x1 << 8) | - (0xF << 4) | (0xF << 0)) : - ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); + 0x11ff : 0xffff; #else - temp = ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); + temp = 0xffff; #endif /* Enable TXDLL */ mrc_alt_write_mask(DDRPHY, - (DQDLLTXCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - temp, 0xFFFF); + DQDLLTXCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + temp, 0xffff); delay_n(3); /* Enable RXDLL */ mrc_alt_write_mask(DDRPHY, - (DQDLLRXCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT3 | BIT2 | BIT1 | BIT0), - (BIT3 | BIT2 | BIT1 | BIT0)); + DQDLLRXCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0xf, 0xf); delay_n(3); /* Enable RXDLL Overrides BL0 */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (BIT3 | BIT2 | BIT1 | BIT0), - (BIT3 | BIT2 | BIT1 | BIT0)); + B0OVRCTL + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0xf, 0xf); } /* ECC */ - temp = ((0xF << 12) | (0xF << 8) | - (0xF << 4) | (0xF << 0)); - mrc_alt_write_mask(DDRPHY, (ECCDLLTXCTL), - temp, 0xFFFF); + temp = 0xffff; + mrc_alt_write_mask(DDRPHY, ECCDLLTXCTL, + temp, 0xffff); delay_n(3); /* CMD (PO) */ mrc_alt_write_mask(DDRPHY, - (CMDDLLTXCTL + (ch * DDRIOCCC_CH_OFFSET)), - temp, 0xFFFF); + CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET, + temp, 0xffff); delay_n(3); } } @@ -1195,94 +1065,85 @@ void ddrphy_init(struct mrc_params *mrc_params) if (mrc_params->channel_enables & (1 << ch)) { /* Host To Memory Clock Alignment (HMC) for 800/1066 */ for (bl_grp = 0; - bl_grp < ((NUM_BYTE_LANES / bl_divisor) / 2); + bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) { /* CLK_ALIGN_MOD_ID */ mrc_alt_write_mask(DDRPHY, - (DQCLKALIGNREG2 + - (bl_grp * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - (bl_grp) ? (0x3) : (0x1), - (BIT3 | BIT2 | BIT1 | BIT0)); + DQCLKALIGNREG2 + + bl_grp * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + bl_grp ? 3 : 1, + 0xf); } mrc_alt_write_mask(DDRPHY, - (ECCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x2, - (BIT3 | BIT2 | BIT1 | BIT0)); + ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x2, 0xf); mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x0, - (BIT3 | BIT2 | BIT1 | BIT0)); + CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x0, 0xf); mrc_alt_write_mask(DDRPHY, - (CCCLKALIGNREG2 + (ch * DDRIODQ_CH_OFFSET)), - 0x2, - (BIT3 | BIT2 | BIT1 | BIT0)); + CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, + 0x2, 0xf); mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)), - (0x2 << 4), (BIT5 | BIT4)); + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, + 0x20, 0x30); /* * NUM_SAMPLES, MAX_SAMPLES, * MACRO_PI_STEP, MICRO_PI_STEP */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG1 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x18 << 16) | (0x10 << 8) | - (0x8 << 2) | (0x1 << 0)), - (BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | - BIT16 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | - BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | - BIT2 | BIT1 | BIT0)); + CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET, + (0x18 << 16) | (0x10 << 8) | + (0x8 << 2) | (0x1 << 0), + 0x007f7fff); /* TOTAL_NUM_MODULES, FIRST_U_PARTITION */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG2 + (ch * DDRIOCCC_CH_OFFSET)), - ((0x10 << 16) | (0x4 << 8) | (0x2 << 4)), - (BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | - BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | - BIT5 | BIT4)); + CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET, + (0x10 << 16) | (0x4 << 8) | (0x2 << 4), + 0x001f0ff0); #ifdef HMC_TEST /* START_CLK_ALIGN=1 */ mrc_alt_write_mask(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT24, BIT24); + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 24, 1 << 24); while (msg_port_alt_read(DDRPHY, - (CMDCLKALIGNREG0 + (ch * DDRIOCCC_CH_OFFSET))) & - BIT24) + CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & + (1 << 24)) ; /* wait for START_CLK_ALIGN=0 */ #endif /* Set RD/WR Pointer Seperation & COUNTEN & FIFOPTREN */ mrc_alt_write_mask(DDRPHY, - (CMDPTRREG + (ch * DDRIOCCC_CH_OFFSET)), - BIT0, BIT0); /* WRPTRENABLE=1 */ + CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, + 1, 1); /* WRPTRENABLE=1 */ /* COMP initial */ /* enable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - BIT5, BIT5); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + 1 << 5, 1 << 5); /* Initial COMP Enable */ - mrc_alt_write_mask(DDRPHY, (CMPCTRL), - (BIT0), (BIT0)); + mrc_alt_write_mask(DDRPHY, CMPCTRL, 1, 1); /* wait for Initial COMP Enable = 0 */ - while (msg_port_alt_read(DDRPHY, (CMPCTRL)) & BIT0) + while (msg_port_alt_read(DDRPHY, CMPCTRL) & 1) ; /* disable bypass for CLK buffer (PO) */ mrc_alt_write_mask(DDRPHY, - (COMPEN0CH0 + (ch * DDRCOMP_CH_OFFSET)), - ~BIT5, BIT5); + COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, + ~(1 << 5), 1 << 5); /* IOBUFACT */ /* STEP4a */ mrc_alt_write_mask(DDRPHY, - (CMDCFGREG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT2, BIT2); /* IOBUFACTRST_N=1 */ + CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 2, 1 << 2); /* IOBUFACTRST_N=1 */ /* DDRPHY initialization complete */ mrc_alt_write_mask(DDRPHY, - (CMDPMCONFIG0 + (ch * DDRIOCCC_CH_OFFSET)), - BIT20, BIT20); /* SPID_INIT_COMPLETE=1 */ + CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, + 1 << 20, 1 << 20); /* SPID_INIT_COMPLETE=1 */ } } @@ -1308,13 +1169,13 @@ void perform_jedec_init(struct mrc_params *mrc_params) mrc_post_code(0x04, 0x00); /* DDR3_RESET_SET=0, DDR3_RESET_RESET=1 */ - mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT1, (BIT8 | BIT1)); + mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 2, 0x102); /* Assert RESET# for 200us */ delay_u(200); /* DDR3_RESET_SET=1, DDR3_RESET_RESET=0 */ - mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, BIT8, (BIT8 | BIT1)); + mrc_alt_write_mask(DDRPHY, CCDDR3RESETCTL, 0x100, 0x102); dtr0 = msg_port_read(MEM_CTLR, DTR0); @@ -1327,8 +1188,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) drp &= 0x3; drmc = msg_port_read(MEM_CTLR, DRMC); - drmc &= 0xFFFFFFFC; - drmc |= (BIT4 | drp); + drmc &= 0xfffffffc; + drmc |= (DRMC_CKEMODE | drp); msg_port_write(MEM_CTLR, DRMC, drmc); @@ -1341,7 +1202,7 @@ void perform_jedec_init(struct mrc_params *mrc_params) } msg_port_write(MEM_CTLR, DRMC, - (mrc_params->rd_odt_value == 0 ? BIT12 : 0)); + (mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0)); /* * setup for emrs 2 @@ -1392,12 +1253,12 @@ void perform_jedec_init(struct mrc_params *mrc_params) * 1** --> RESERVED */ emrs1_cmd |= (1 << 3); - emrs1_cmd &= ~BIT6; + emrs1_cmd &= ~(1 << 6); if (mrc_params->ron_value == 0) - emrs1_cmd |= BIT7; + emrs1_cmd |= (1 << 7); else - emrs1_cmd &= ~BIT7; + emrs1_cmd &= ~(1 << 7); if (mrc_params->rtt_nom_value == 0) emrs1_cmd |= (DDR3_EMRS1_RTTNOM_40 << 6); @@ -1432,8 +1293,8 @@ void perform_jedec_init(struct mrc_params *mrc_params) * BIT[02:02] "0" if oem_tCAS <= 11 (1866?) * BIT[06:04] use oem_tCAS-4 */ - mrs0_cmd |= BIT14; - mrs0_cmd |= BIT18; + mrs0_cmd |= (1 << 14); + mrs0_cmd |= (1 << 18); mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10); tck = t_ck[mrc_params->ddr_speed]; @@ -1480,8 +1341,8 @@ void set_ddr_init_complete(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT28; - dco |= BIT31; + dco &= ~DCO_PMICTL; + dco |= DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -1577,7 +1438,7 @@ void rcvn_cal(struct mrc_params *mrc_params) /* need separate burst to sample DQS preamble */ dtr1 = msg_port_read(MEM_CTLR, DTR1); dtr1_save = dtr1; - dtr1 |= BIT12; + dtr1 |= DTR1_TCCD_12CLK; msg_port_write(MEM_CTLR, DTR1, dtr1); #endif @@ -1596,7 +1457,7 @@ void rcvn_cal(struct mrc_params *mrc_params) * POST_CODE here indicates the current * channel and rank being calibrated */ - mrc_post_code(0x05, (0x10 + ((ch << 4) | rk))); + mrc_post_code(0x05, 0x10 + ((ch << 4) | rk)); #ifdef BACKUP_RCVN /* et hard-coded timing values */ @@ -1606,10 +1467,10 @@ void rcvn_cal(struct mrc_params *mrc_params) /* enable FIFORST */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - ((bl >> 1) * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - 0, BIT8); + B01PTRCTL1 + + (bl >> 1) * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 0, 1 << 8); } /* initialize the starting delay to 128 PI (cas +1 CLK) */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { @@ -1638,11 +1499,11 @@ void rcvn_cal(struct mrc_params *mrc_params) } else { /* not enough delay */ training_message(ch, rk, bl); - mrc_post_code(0xEE, 0x50); + mrc_post_code(0xee, 0x50); } } } - } while (temp & 0xFF); + } while (temp & 0xff); #ifdef R2R_SHARING /* increment "num_ranks_enabled" */ @@ -1653,7 +1514,7 @@ void rcvn_cal(struct mrc_params *mrc_params) /* add "delay[]" values to "final_delay[][]" for rolling average */ final_delay[ch][bl] += delay[bl]; /* set timing based on rolling average values */ - set_rcvn(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); } #else /* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */ @@ -1666,10 +1527,10 @@ void rcvn_cal(struct mrc_params *mrc_params) /* disable FIFORST */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl += 2) { mrc_alt_write_mask(DDRPHY, - (B01PTRCTL1 + - ((bl >> 1) * DDRIODQ_BL_OFFSET) + - (ch * DDRIODQ_CH_OFFSET)), - BIT8, BIT8); + B01PTRCTL1 + + (bl >> 1) * DDRIODQ_BL_OFFSET + + ch * DDRIODQ_CH_OFFSET, + 1 << 8, 1 << 8); } #endif } @@ -1742,12 +1603,12 @@ void wr_level(struct mrc_params *mrc_params) * POST_CODE here indicates the current * rank and channel being calibrated */ - mrc_post_code(0x06, (0x10 + ((ch << 4) | rk))); + mrc_post_code(0x06, 0x10 + ((ch << 4) | rk)); #ifdef BACKUP_WDQS for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); - set_wdq(ch, rk, bl, (ddr_wdqs[PLATFORM_ID] - QRTR_CLK)); + set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); } #else /* @@ -1760,7 +1621,7 @@ void wr_level(struct mrc_params *mrc_params) * enable Write Levelling Mode * (EMRS1 w/ Write Levelling Mode Enable) */ - dram_init_command(DCMD_MRS1(rk, 0x0082)); + dram_init_command(DCMD_MRS1(rk, 0x82)); /* * set ODT DRAM Full Time Termination @@ -1769,24 +1630,24 @@ void wr_level(struct mrc_params *mrc_params) dtr4 = msg_port_read(MEM_CTLR, DTR4); dtr4_save = dtr4; - dtr4 |= BIT15; + dtr4 |= DTR4_ODTDIS; msg_port_write(MEM_CTLR, DTR4, dtr4); - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* * Enable Sandy Bridge Mode (WDQ Tri-State) & * Ensure 5 WDQS pulses during Write Leveling */ mrc_alt_write_mask(DDRPHY, - DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch), - (BIT28 | BIT8 | BIT6 | BIT4 | BIT2), - (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, + 0x10000154, + 0x100003fc); } /* Write Leveling Mode enabled in IO */ mrc_alt_write_mask(DDRPHY, - CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch), - BIT16, BIT16); + CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, + 1 << 16, 1 << 16); /* Initialize the starting delay to WCLK */ for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { @@ -1804,15 +1665,15 @@ void wr_level(struct mrc_params *mrc_params) /* disable Write Levelling Mode */ mrc_alt_write_mask(DDRPHY, - CCDDR3RESETCTL + (DDRIOCCC_CH_OFFSET * ch), - 0, BIT16); + CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, + 0, 1 << 16); - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* Disable Sandy Bridge Mode & Ensure 4 WDQS pulses during normal operation */ mrc_alt_write_mask(DDRPHY, - DQCTL + (DDRIODQ_BL_OFFSET * bl) + (DDRIODQ_CH_OFFSET * ch), - (BIT8 | BIT6 | BIT4 | BIT2), - (BIT28 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2)); + DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, + 0x00000154, + 0x100003fc); } /* restore original DTR4 */ @@ -1830,7 +1691,7 @@ void wr_level(struct mrc_params *mrc_params) */ dram_init_command(DCMD_PREA(rk)); - mrc_post_code(0x06, (0x30 + ((ch << 4) | rk))); + mrc_post_code(0x06, 0x30 + ((ch << 4) | rk)); /* * COARSE WRITE LEVEL: @@ -1863,13 +1724,13 @@ void wr_level(struct mrc_params *mrc_params) coarse_result = check_rw_coarse(mrc_params, address); /* check for failures and margin the byte lane back 128 PI (1 CLK) */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (coarse_result & (coarse_result_mask << bl)) { all_edges_found = false; delay[bl] -= FULL_CLK; set_wdqs(ch, rk, bl, delay[bl]); /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ - set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); + set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); } } } while (!all_edges_found); @@ -1878,11 +1739,11 @@ void wr_level(struct mrc_params *mrc_params) /* increment "num_ranks_enabled" */ num_ranks_enabled++; /* accumulate "final_delay[][]" values from "delay[]" values for rolling average */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { final_delay[ch][bl] += delay[bl]; - set_wdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ - set_wdq(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled) - QRTR_CLK); + set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); } #endif #endif @@ -1901,9 +1762,9 @@ void prog_page_ctrl(struct mrc_params *mrc_params) ENTERFN(); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 &= ~(BIT16 | BIT17 | BIT18); + dpmc0 &= ~DPMC0_PCLSTO_MASK; dpmc0 |= (4 << 16); - dpmc0 |= BIT21; + dpmc0 |= DPMC0_PREAPWDEN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); } @@ -1966,7 +1827,7 @@ void rd_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); } @@ -1981,7 +1842,7 @@ void rd_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* x_coordinate */ x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; @@ -2011,7 +1872,7 @@ void rd_train(struct mrc_params *mrc_params) /* look for passing coordinates */ for (side_y = B; side_y <= T; side_y++) { for (side_x = L; side_x <= R; side_x++) { - mrc_post_code(0x07, (0x10 + (side_y * 2) + (side_x))); + mrc_post_code(0x07, 0x10 + side_y * 2 + side_x); /* find passing values */ for (ch = 0; ch < NUM_CHANNELS; ch++) { @@ -2021,7 +1882,7 @@ void rd_train(struct mrc_params *mrc_params) (0x1 << rk)) { /* set x/y_coordinate search starting settings */ for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); @@ -2041,9 +1902,9 @@ void rd_train(struct mrc_params *mrc_params) result = check_bls_ex(mrc_params, address); /* check for failures */ - if (result & 0xFF) { + if (result & 0xff) { /* at least 1 byte lane failed */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (result & (bl_mask << bl)) { /* adjust the RDQS values accordingly */ @@ -2072,13 +1933,13 @@ void rd_train(struct mrc_params *mrc_params) (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { /* VREF_EYE collapsed below MIN_VREF_EYE */ training_message(ch, rk, bl); - mrc_post_code(0xEE, (0x70 + (side_y * 2) + (side_x))); + mrc_post_code(0xEE, 0x70 + side_y * 2 + side_x); } else { /* update the VREF setting */ set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); /* reset the X coordinate to begin the search at the new VREF */ x_coordinate[side_x][side_y][ch][rk][bl] = - (side_x == L) ? (RDQS_MIN) : (RDQS_MAX); + (side_x == L) ? RDQS_MIN : RDQS_MAX; } } @@ -2087,7 +1948,7 @@ void rd_train(struct mrc_params *mrc_params) } } } - } while (result & 0xFF); + } while (result & 0xff); } } } @@ -2147,23 +2008,23 @@ void rd_train(struct mrc_params *mrc_params) /* perform an eye check */ for (side_y = B; side_y <= T; side_y++) { for (side_x = L; side_x <= R; side_x++) { - mrc_post_code(0x07, (0x30 + (side_y * 2) + (side_x))); + mrc_post_code(0x07, 0x30 + side_y * 2 + side_x); /* update the settings for the eye check */ for (ch = 0; ch < NUM_CHANNELS; ch++) { if (mrc_params->channel_enables & (1 << ch)) { for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (side_x == L) - set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2))); + set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); else - set_rdqs(ch, rk, bl, (x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2))); + set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); if (side_y == B) - set_vref(ch, bl, (y_center[ch][bl] - (MIN_VREF_EYE / 2))); + set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); else - set_vref(ch, bl, (y_center[ch][bl] + (MIN_VREF_EYE / 2))); + set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); } } } @@ -2174,9 +2035,9 @@ void rd_train(struct mrc_params *mrc_params) mrc_params->hte_setup = 1; /* check the eye */ - if (check_bls_ex(mrc_params, address) & 0xFF) { + if (check_bls_ex(mrc_params, address) & 0xff) { /* one or more byte lanes failed */ - mrc_post_code(0xEE, (0x74 + (side_x * 2) + (side_y))); + mrc_post_code(0xee, 0x74 + side_x * 2 + side_y); } } } @@ -2197,7 +2058,7 @@ void rd_train(struct mrc_params *mrc_params) /* x_coordinate */ #ifdef R2R_SHARING final_delay[ch][bl] += x_center[ch][rk][bl]; - set_rdqs(ch, rk, bl, ((final_delay[ch][bl]) / num_ranks_enabled)); + set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); #else set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); #endif @@ -2258,7 +2119,7 @@ void wr_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); } @@ -2273,7 +2134,7 @@ void wr_train(struct mrc_params *mrc_params) for (rk = 0; rk < NUM_RANKS; rk++) { if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { /* * want to start with @@ -2303,7 +2164,7 @@ void wr_train(struct mrc_params *mrc_params) * until no failures are observed, then repeat for the RIGHT side. */ for (side = L; side <= R; side++) { - mrc_post_code(0x08, (0x10 + (side))); + mrc_post_code(0x08, 0x10 + side); /* set starting values */ for (ch = 0; ch < NUM_CHANNELS; ch++) { @@ -2312,7 +2173,7 @@ void wr_train(struct mrc_params *mrc_params) if (mrc_params->rank_enables & (1 << rk)) { for (bl = 0; - bl < (NUM_BYTE_LANES / bl_divisor); + bl < NUM_BYTE_LANES / bl_divisor; bl++) { set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); } @@ -2338,9 +2199,9 @@ void wr_train(struct mrc_params *mrc_params) /* result[07:00] == failing byte lane (MAX 8) */ result = check_bls_ex(mrc_params, address); /* check for failures */ - if (result & 0xFF) { + if (result & 0xff) { /* at least 1 byte lane failed */ - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { if (result & (bl_mask << bl)) { if (side == L) @@ -2362,13 +2223,13 @@ void wr_train(struct mrc_params *mrc_params) * notify the user and halt */ training_message(ch, rk, bl); - mrc_post_code(0xEE, (0x80 + side)); + mrc_post_code(0xee, 0x80 + side); } } } } /* stop when all byte lanes pass */ - } while (result & 0xFF); + } while (result & 0xff); } } } @@ -2384,7 +2245,7 @@ void wr_train(struct mrc_params *mrc_params) /* increment "num_ranks_enabled" */ num_ranks_enabled++; #endif - for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) { + for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) { DPF(D_INFO, "WDQ eye rank%d lane%d : %d-%d\n", rk, bl, @@ -2396,7 +2257,7 @@ void wr_train(struct mrc_params *mrc_params) #ifdef R2R_SHARING final_delay[ch][bl] += temp; set_wdq(ch, rk, bl, - ((final_delay[ch][bl]) / num_ranks_enabled)); + final_delay[ch][bl] / num_ranks_enabled); #else set_wdq(ch, rk, bl, temp); #endif @@ -2470,7 +2331,7 @@ void enable_scrambling(struct mrc_params *mrc_params) * get seed from system clock * and make sure it is not all 1's */ - lfsr = rdtsc() & 0x0FFFFFFF; + lfsr = rdtsc() & 0x0fffffff; } else { /* * Need to replace scrambler @@ -2491,10 +2352,10 @@ void enable_scrambling(struct mrc_params *mrc_params) * In cold boot, we have the last 32bit LFSR which is the new seed. */ lfsr32(&lfsr); /* shift to next value */ - msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003FFFF)); + msg_port_write(MEM_CTLR, SCRMSEED, (lfsr & 0x0003ffff)); for (i = 0; i < 2; i++) - msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xAAAAAAAA)); + msg_port_write(MEM_CTLR, SCRMLO + i, (lfsr & 0xaaaaaaaa)); LEAVEFN(); } @@ -2511,20 +2372,20 @@ void prog_ddr_control(struct mrc_params *mrc_params) ENTERFN(); dsch = msg_port_read(MEM_CTLR, DSCH); - dsch &= ~(BIT8 | BIT9 | BIT12); + dsch &= ~(DSCH_OOODIS | DSCH_OOOST3DIS | DSCH_NEWBYPDIS); msg_port_write(MEM_CTLR, DSCH, dsch); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 &= ~BIT25; + dpmc0 &= ~DPMC0_DISPWRDN; dpmc0 |= (mrc_params->power_down_disable << 25); - dpmc0 &= ~BIT24; - dpmc0 &= ~(BIT16 | BIT17 | BIT18); + dpmc0 &= ~DPMC0_CLKGTDIS; + dpmc0 &= ~DPMC0_PCLSTO_MASK; dpmc0 |= (4 << 16); - dpmc0 |= BIT21; + dpmc0 |= DPMC0_PREAPWDEN; msg_port_write(MEM_CTLR, DPMC0, dpmc0); /* CMDTRIST = 2h - CMD/ADDR are tristated when no valid command */ - mrc_write_mask(MEM_CTLR, DPMC1, 2 << 4, BIT4 | BIT5); + mrc_write_mask(MEM_CTLR, DPMC1, 0x20, 0x30); LEAVEFN(); } @@ -2542,14 +2403,14 @@ void prog_dra_drb(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~BIT31; + dco &= ~DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); drp = 0; if (mrc_params->rank_enables & 1) - drp |= BIT0; + drp |= DRP_RKEN0; if (mrc_params->rank_enables & 2) - drp |= BIT1; + drp |= DRP_RKEN1; if (mrc_params->dram_width == X16) { drp |= (1 << 4); drp |= (1 << 9); @@ -2570,8 +2431,8 @@ void prog_dra_drb(struct mrc_params *mrc_params) msg_port_write(MEM_CTLR, DRP, drp); - dco &= ~BIT28; - dco |= BIT31; + dco &= ~DCO_PMICTL; + dco |= DCO_IC; msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); @@ -2600,18 +2461,18 @@ void change_refresh_period(struct mrc_params *mrc_params) ENTERFN(); drfc = msg_port_read(MEM_CTLR, DRFC); - drfc &= ~(BIT12 | BIT13 | BIT14); + drfc &= ~DRFC_TREFI_MASK; drfc |= (mrc_params->refresh_rate << 12); - drfc |= BIT21; + drfc |= DRFC_REFDBTCLR; msg_port_write(MEM_CTLR, DRFC, drfc); dcal = msg_port_read(MEM_CTLR, DCAL); - dcal &= ~(BIT8 | BIT9 | BIT10); + dcal &= ~DCAL_ZQCINT_MASK; dcal |= (3 << 8); /* 63ms */ msg_port_write(MEM_CTLR, DCAL, dcal); dpmc0 = msg_port_read(MEM_CTLR, DPMC0); - dpmc0 |= (BIT23 | BIT29); + dpmc0 |= (DPMC0_DYNSREN | DPMC0_ENPHYCLKGATE); msg_port_write(MEM_CTLR, DPMC0, dpmc0); LEAVEFN(); @@ -2638,36 +2499,32 @@ void set_auto_refresh(struct mrc_params *mrc_params) for (channel = 0; channel < NUM_CHANNELS; channel++) { if (mrc_params->channel_enables & (1 << channel)) { /* Enable Periodic RCOMPS */ - mrc_alt_write_mask(DDRPHY, CMPCTRL, BIT1, BIT1); + mrc_alt_write_mask(DDRPHY, CMPCTRL, 2, 2); /* Enable Dynamic DiffAmp & Set Read ODT Value */ switch (mrc_params->rd_odt_value) { case 0: - temp = 0x3F; /* OFF */ + temp = 0x3f; /* OFF */ break; default: temp = 0x00; /* Auto */ break; } - for (bl = 0; bl < ((NUM_BYTE_LANES / bl_divisor) / 2); bl++) { + for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor) / 2; bl++) { /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B0OVRCTL + (bl * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)), - (0x00 << 16) | (temp << 10), - (BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10)); + B0OVRCTL + bl * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET, + temp << 10, + 0x003ffc00); /* Override: DIFFAMP, ODT */ mrc_alt_write_mask(DDRPHY, - (B1OVRCTL + (bl * DDRIODQ_BL_OFFSET) + - (channel * DDRIODQ_CH_OFFSET)), - (0x00 << 16) | (temp << 10), - (BIT21 | BIT20 | BIT19 | BIT18 | - BIT17 | BIT16 | BIT15 | BIT14 | - BIT13 | BIT12 | BIT11 | BIT10)); + B1OVRCTL + bl * DDRIODQ_BL_OFFSET + + channel * DDRIODQ_CH_OFFSET, + temp << 10, + 0x003ffc00); } /* Issue ZQCS command */ @@ -2702,18 +2559,18 @@ void ecc_enable(struct mrc_params *mrc_params) /* Configuration required in ECC mode */ drp = msg_port_read(MEM_CTLR, DRP); - drp &= ~(BIT14 | BIT15); - drp |= BIT15; - drp |= BIT13; + drp &= ~DRP_ADDRMAP_MASK; + drp |= DRP_ADDRMAP_MAP1; + drp |= DRP_PRI64BSPLITEN; msg_port_write(MEM_CTLR, DRP, drp); /* Disable new request bypass */ dsch = msg_port_read(MEM_CTLR, DSCH); - dsch |= BIT12; + dsch |= DSCH_NEWBYPDIS; msg_port_write(MEM_CTLR, DSCH, dsch); /* Enable ECC */ - ecc_ctrl = (BIT0 | BIT1 | BIT17); + ecc_ctrl = (DECCCTRL_SBEEN | DECCCTRL_DBEEN | DECCCTRL_ENCBGEN); msg_port_write(MEM_CTLR, DECCCTRL, ecc_ctrl); /* Assume 8 bank memory, one bank is gone for ECC */ @@ -2756,8 +2613,8 @@ void lock_registers(struct mrc_params *mrc_params) ENTERFN(); dco = msg_port_read(MEM_CTLR, DCO); - dco &= ~(BIT28 | BIT29); - dco |= (BIT0 | BIT8); + dco &= ~(DCO_PMICTL | DCO_PMIDIS); + dco |= (DCO_DRPLOCK | DCO_CPGCLOCK); msg_port_write(MEM_CTLR, DCO, dco); LEAVEFN(); diff --git a/arch/x86/cpu/quark/smc.h b/arch/x86/cpu/quark/smc.h index 46017a1ccb..1582b87e10 100644 --- a/arch/x86/cpu/quark/smc.h +++ b/arch/x86/cpu/quark/smc.h @@ -24,46 +24,133 @@ #define DPMC1 0x07 #define DRFC 0x08 #define DSCH 0x09 -#define DCAL 0x0A -#define DRMC 0x0B -#define PMSTS 0x0C -#define DCO 0x0F +#define DCAL 0x0a +#define DRMC 0x0b +#define PMSTS 0x0c +#define DCO 0x0f #define DSTAT 0x20 -#define SSKPD0 0x4A -#define SSKPD1 0x4B +#define SSKPD0 0x4a +#define SSKPD1 0x4b #define DECCCTRL 0x60 #define DECCSTAT 0x61 #define DECCSBECNT 0x62 #define DECCSBECA 0x68 #define DECCSBECS 0x69 -#define DECCDBECA 0x6A -#define DECCDBECS 0x6B +#define DECCDBECA 0x6a +#define DECCDBECS 0x6b #define DFUSESTAT 0x70 #define SCRMSEED 0x80 #define SCRMLO 0x81 #define SCRMHI 0x82 +/* DRP register defines */ +#define DRP_RKEN0 (1 << 0) +#define DRP_RKEN1 (1 << 1) +#define DRP_PRI64BSPLITEN (1 << 13) +#define DRP_ADDRMAP_MAP0 (1 << 14) +#define DRP_ADDRMAP_MAP1 (1 << 15) +#define DRP_ADDRMAP_MASK 0x0000c000 + +/* DTR0 register defines */ +#define DTR0_DFREQ_MASK 0x00000003 +#define DTR0_TRP_MASK 0x000000f0 +#define DTR0_TRCD_MASK 0x00000f00 +#define DTR0_TCL_MASK 0x00007000 + +/* DTR1 register defines */ +#define DTR1_TWCL_MASK 0x00000007 +#define DTR1_TCMD_MASK 0x00000030 +#define DTR1_TWTP_MASK 0x00000f00 +#define DTR1_TCCD_12CLK (1 << 12) +#define DTR1_TCCD_18CLK (1 << 13) +#define DTR1_TCCD_MASK 0x00003000 +#define DTR1_TFAW_MASK 0x000f0000 +#define DTR1_TRAS_MASK 0x00f00000 +#define DTR1_TRRD_MASK 0x03000000 +#define DTR1_TRTP_MASK 0x70000000 + +/* DTR2 register defines */ +#define DTR2_TRRDR_MASK 0x00000007 +#define DTR2_TWWDR_MASK 0x00000700 +#define DTR2_TRWDR_MASK 0x000f0000 + +/* DTR3 register defines */ +#define DTR3_TWRDR_MASK 0x00000007 +#define DTR3_TXXXX_MASK 0x00000070 +#define DTR3_TRWSR_MASK 0x00000f00 +#define DTR3_TWRSR_MASK 0x0001e000 +#define DTR3_TXP_MASK 0x00c00000 + +/* DTR4 register defines */ +#define DTR4_WRODTSTRT_MASK 0x00000003 +#define DTR4_WRODTSTOP_MASK 0x00000070 +#define DTR4_XXXX1_MASK 0x00000700 +#define DTR4_XXXX2_MASK 0x00007000 +#define DTR4_ODTDIS (1 << 15) +#define DTR4_TRGSTRDIS (1 << 16) + +/* DPMC0 register defines */ +#define DPMC0_PCLSTO_MASK 0x00070000 +#define DPMC0_PREAPWDEN (1 << 21) +#define DPMC0_DYNSREN (1 << 23) +#define DPMC0_CLKGTDIS (1 << 24) +#define DPMC0_DISPWRDN (1 << 25) +#define DPMC0_ENPHYCLKGATE (1 << 29) + +/* DRFC register defines */ +#define DRFC_TREFI_MASK 0x00007000 +#define DRFC_REFDBTCLR (1 << 21) + +/* DSCH register defines */ +#define DSCH_OOODIS (1 << 8) +#define DSCH_OOOST3DIS (1 << 9) +#define DSCH_NEWBYPDIS (1 << 12) + +/* DCAL register defines */ +#define DCAL_ZQCINT_MASK 0x00000700 +#define DCAL_SRXZQCL_MASK 0x00003000 + +/* DRMC register defines */ +#define DRMC_CKEMODE (1 << 4) +#define DRMC_ODTMODE (1 << 12) +#define DRMC_COLDWAKE (1 << 16) + +/* PMSTS register defines */ +#define PMSTS_DISR (1 << 0) + +/* DCO register defines */ +#define DCO_DRPLOCK (1 << 0) +#define DCO_CPGCLOCK (1 << 8) +#define DCO_PMICTL (1 << 28) +#define DCO_PMIDIS (1 << 29) +#define DCO_IC (1 << 31) + +/* DECCCTRL register defines */ +#define DECCCTRL_SBEEN (1 << 0) +#define DECCCTRL_DBEEN (1 << 1) +#define DECCCTRL_ENCBGEN (1 << 17) + /* DRAM init command */ #define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6)) #define DCMD_REF(rnk) (1 | ((rnk) << 22)) #define DCMD_PRE(rnk) (2 | ((rnk) << 22)) -#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (BIT10 << 6)) +#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6)) #define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6)) #define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6)) #define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6)) #define DCMD_ZQCS(rnk) (6 | ((rnk) << 22)) -#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (BIT10 << 6)) +#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (0x400 << 6)) #define DCMD_NOP(rnk) (7 | ((rnk) << 22)) -#define DDR3_EMRS1_DIC_40 (0) -#define DDR3_EMRS1_DIC_34 (1) +#define DDR3_EMRS1_DIC_40 0 +#define DDR3_EMRS1_DIC_34 1 -#define DDR3_EMRS1_RTTNOM_0 (0) -#define DDR3_EMRS1_RTTNOM_60 (0x04) -#define DDR3_EMRS1_RTTNOM_120 (0x40) -#define DDR3_EMRS1_RTTNOM_40 (0x44) -#define DDR3_EMRS1_RTTNOM_20 (0x200) -#define DDR3_EMRS1_RTTNOM_30 (0x204) +#define DDR3_EMRS1_RTTNOM_0 0 +#define DDR3_EMRS1_RTTNOM_60 0x04 +#define DDR3_EMRS1_RTTNOM_120 0x40 +#define DDR3_EMRS1_RTTNOM_40 0x44 +#define DDR3_EMRS1_RTTNOM_20 0x200 +#define DDR3_EMRS1_RTTNOM_30 0x204 #define DDR3_EMRS2_RTTWR_60 (1 << 9) #define DDR3_EMRS2_RTTWR_120 (1 << 10) @@ -80,87 +167,87 @@ #define DQOBSCKEBBCTL 0x0000 #define DQDLLTXCTL 0x0004 #define DQDLLRXCTL 0x0008 -#define DQMDLLCTL 0x000C +#define DQMDLLCTL 0x000c #define B0RXIOBUFCTL 0x0010 #define B0VREFCTL 0x0014 #define B0RXOFFSET1 0x0018 -#define B0RXOFFSET0 0x001C +#define B0RXOFFSET0 0x001c #define B1RXIOBUFCTL 0x0020 #define B1VREFCTL 0x0024 #define B1RXOFFSET1 0x0028 -#define B1RXOFFSET0 0x002C +#define B1RXOFFSET0 0x002c #define DQDFTCTL 0x0030 #define DQTRAINSTS 0x0034 #define B1DLLPICODER0 0x0038 -#define B0DLLPICODER0 0x003C +#define B0DLLPICODER0 0x003c #define B1DLLPICODER1 0x0040 #define B0DLLPICODER1 0x0044 #define B1DLLPICODER2 0x0048 -#define B0DLLPICODER2 0x004C +#define B0DLLPICODER2 0x004c #define B1DLLPICODER3 0x0050 #define B0DLLPICODER3 0x0054 #define B1RXDQSPICODE 0x0058 -#define B0RXDQSPICODE 0x005C +#define B0RXDQSPICODE 0x005c #define B1RXDQPICODER32 0x0060 #define B1RXDQPICODER10 0x0064 #define B0RXDQPICODER32 0x0068 -#define B0RXDQPICODER10 0x006C +#define B0RXDQPICODER10 0x006c #define B01PTRCTL0 0x0070 #define B01PTRCTL1 0x0074 #define B01DBCTL0 0x0078 -#define B01DBCTL1 0x007C +#define B01DBCTL1 0x007c #define B0LATCTL0 0x0080 #define B1LATCTL0 0x0084 #define B01LATCTL1 0x0088 -#define B0ONDURCTL 0x008C +#define B0ONDURCTL 0x008c #define B1ONDURCTL 0x0090 #define B0OVRCTL 0x0094 #define B1OVRCTL 0x0098 -#define DQCTL 0x009C -#define B0RK2RKCHGPTRCTRL 0x00A0 -#define B1RK2RKCHGPTRCTRL 0x00A4 -#define DQRK2RKCTL 0x00A8 -#define DQRK2RKPTRCTL 0x00AC -#define B0RK2RKLAT 0x00B0 -#define B1RK2RKLAT 0x00B4 -#define DQCLKALIGNREG0 0x00B8 -#define DQCLKALIGNREG1 0x00BC -#define DQCLKALIGNREG2 0x00C0 -#define DQCLKALIGNSTS0 0x00C4 -#define DQCLKALIGNSTS1 0x00C8 -#define DQCLKGATE 0x00CC -#define B0COMPSLV1 0x00D0 -#define B1COMPSLV1 0x00D4 -#define B0COMPSLV2 0x00D8 -#define B1COMPSLV2 0x00DC -#define B0COMPSLV3 0x00E0 -#define B1COMPSLV3 0x00E4 -#define DQVISALANECR0TOP 0x00E8 -#define DQVISALANECR1TOP 0x00EC -#define DQVISACONTROLCRTOP 0x00F0 -#define DQVISALANECR0BL 0x00F4 -#define DQVISALANECR1BL 0x00F8 -#define DQVISACONTROLCRBL 0x00FC -#define DQTIMINGCTRL 0x010C +#define DQCTL 0x009c +#define B0RK2RKCHGPTRCTRL 0x00a0 +#define B1RK2RKCHGPTRCTRL 0x00a4 +#define DQRK2RKCTL 0x00a8 +#define DQRK2RKPTRCTL 0x00ac +#define B0RK2RKLAT 0x00b0 +#define B1RK2RKLAT 0x00b4 +#define DQCLKALIGNREG0 0x00b8 +#define DQCLKALIGNREG1 0x00bc +#define DQCLKALIGNREG2 0x00c0 +#define DQCLKALIGNSTS0 0x00c4 +#define DQCLKALIGNSTS1 0x00c8 +#define DQCLKGATE 0x00cc +#define B0COMPSLV1 0x00d0 +#define B1COMPSLV1 0x00d4 +#define B0COMPSLV2 0x00d8 +#define B1COMPSLV2 0x00dc +#define B0COMPSLV3 0x00e0 +#define B1COMPSLV3 0x00e4 +#define DQVISALANECR0TOP 0x00e8 +#define DQVISALANECR1TOP 0x00ec +#define DQVISACONTROLCRTOP 0x00f0 +#define DQVISALANECR0BL 0x00f4 +#define DQVISALANECR1BL 0x00f8 +#define DQVISACONTROLCRBL 0x00fc +#define DQTIMINGCTRL 0x010c /* CH0-ECC */ #define ECCDLLTXCTL 0x2004 #define ECCDLLRXCTL 0x2008 -#define ECCMDLLCTL 0x200C +#define ECCMDLLCTL 0x200c #define ECCB1DLLPICODER0 0x2038 #define ECCB1DLLPICODER1 0x2040 #define ECCB1DLLPICODER2 0x2048 #define ECCB1DLLPICODER3 0x2050 #define ECCB01DBCTL0 0x2078 -#define ECCB01DBCTL1 0x207C -#define ECCCLKALIGNREG0 0x20B8 -#define ECCCLKALIGNREG1 0x20BC -#define ECCCLKALIGNREG2 0x20C0 +#define ECCB01DBCTL1 0x207c +#define ECCCLKALIGNREG0 0x20b8 +#define ECCCLKALIGNREG1 0x20bc +#define ECCCLKALIGNREG2 0x20c0 /* CH0-CMD */ #define CMDOBSCKEBBCTL 0x4800 #define CMDDLLTXCTL 0x4808 -#define CMDDLLRXCTL 0x480C +#define CMDDLLRXCTL 0x480c #define CMDMDLLCTL 0x4810 #define CMDRCOMPODT 0x4814 #define CMDDLLPICODER0 0x4820 @@ -170,30 +257,30 @@ #define CMDCLKALIGNREG0 0x4850 #define CMDCLKALIGNREG1 0x4854 #define CMDCLKALIGNREG2 0x4858 -#define CMDPMCONFIG0 0x485C +#define CMDPMCONFIG0 0x485c #define CMDPMDLYREG0 0x4860 #define CMDPMDLYREG1 0x4864 #define CMDPMDLYREG2 0x4868 -#define CMDPMDLYREG3 0x486C +#define CMDPMDLYREG3 0x486c #define CMDPMDLYREG4 0x4870 #define CMDCLKALIGNSTS0 0x4874 #define CMDCLKALIGNSTS1 0x4878 -#define CMDPMSTS0 0x487C +#define CMDPMSTS0 0x487c #define CMDPMSTS1 0x4880 #define CMDCOMPSLV 0x4884 -#define CMDBONUS0 0x488C +#define CMDBONUS0 0x488c #define CMDBONUS1 0x4890 #define CMDVISALANECR0 0x4894 #define CMDVISALANECR1 0x4898 -#define CMDVISACONTROLCR 0x489C -#define CMDCLKGATE 0x48A0 -#define CMDTIMINGCTRL 0x48A4 +#define CMDVISACONTROLCR 0x489c +#define CMDCLKGATE 0x48a0 +#define CMDTIMINGCTRL 0x48a4 /* CH0-CLK-CTL */ #define CCOBSCKEBBCTL 0x5800 #define CCRCOMPIO 0x5804 #define CCDLLTXCTL 0x5808 -#define CCDLLRXCTL 0x580C +#define CCDLLRXCTL 0x580c #define CCMDLLCTL 0x5810 #define CCRCOMPODT 0x5814 #define CCDLLPICODER0 0x5820 @@ -205,123 +292,123 @@ #define CCCLKALIGNREG0 0x5850 #define CCCLKALIGNREG1 0x5854 #define CCCLKALIGNREG2 0x5858 -#define CCPMCONFIG0 0x585C +#define CCPMCONFIG0 0x585c #define CCPMDLYREG0 0x5860 #define CCPMDLYREG1 0x5864 #define CCPMDLYREG2 0x5868 -#define CCPMDLYREG3 0x586C +#define CCPMDLYREG3 0x586c #define CCPMDLYREG4 0x5870 #define CCCLKALIGNSTS0 0x5874 #define CCCLKALIGNSTS1 0x5878 -#define CCPMSTS0 0x587C +#define CCPMSTS0 0x587c #define CCPMSTS1 0x5880 #define CCCOMPSLV1 0x5884 #define CCCOMPSLV2 0x5888 -#define CCCOMPSLV3 0x588C +#define CCCOMPSLV3 0x588c #define CCBONUS0 0x5894 #define CCBONUS1 0x5898 -#define CCVISALANECR0 0x589C -#define CCVISALANECR1 0x58A0 -#define CCVISACONTROLCR 0x58A4 -#define CCCLKGATE 0x58A8 -#define CCTIMINGCTL 0x58AC +#define CCVISALANECR0 0x589c +#define CCVISALANECR1 0x58a0 +#define CCVISACONTROLCR 0x58a4 +#define CCCLKGATE 0x58a8 +#define CCTIMINGCTL 0x58ac /* COMP */ #define CMPCTRL 0x6800 #define SOFTRSTCNTL 0x6804 #define MSCNTR 0x6808 -#define NMSCNTRL 0x680C +#define NMSCNTRL 0x680c #define LATCH1CTL 0x6814 -#define COMPVISALANECR0 0x681C +#define COMPVISALANECR0 0x681c #define COMPVISALANECR1 0x6820 #define COMPVISACONTROLCR 0x6824 #define COMPBONUS0 0x6830 -#define TCOCNTCTRL 0x683C +#define TCOCNTCTRL 0x683c #define DQANAODTPUCTL 0x6840 #define DQANAODTPDCTL 0x6844 #define DQANADRVPUCTL 0x6848 -#define DQANADRVPDCTL 0x684C +#define DQANADRVPDCTL 0x684c #define DQANADLYPUCTL 0x6850 #define DQANADLYPDCTL 0x6854 #define DQANATCOPUCTL 0x6858 -#define DQANATCOPDCTL 0x685C +#define DQANATCOPDCTL 0x685c #define CMDANADRVPUCTL 0x6868 -#define CMDANADRVPDCTL 0x686C +#define CMDANADRVPDCTL 0x686c #define CMDANADLYPUCTL 0x6870 #define CMDANADLYPDCTL 0x6874 #define CLKANAODTPUCTL 0x6880 #define CLKANAODTPDCTL 0x6884 #define CLKANADRVPUCTL 0x6888 -#define CLKANADRVPDCTL 0x688C +#define CLKANADRVPDCTL 0x688c #define CLKANADLYPUCTL 0x6890 #define CLKANADLYPDCTL 0x6894 #define CLKANATCOPUCTL 0x6898 -#define CLKANATCOPDCTL 0x689C -#define DQSANAODTPUCTL 0x68A0 -#define DQSANAODTPDCTL 0x68A4 -#define DQSANADRVPUCTL 0x68A8 -#define DQSANADRVPDCTL 0x68AC -#define DQSANADLYPUCTL 0x68B0 -#define DQSANADLYPDCTL 0x68B4 -#define DQSANATCOPUCTL 0x68B8 -#define DQSANATCOPDCTL 0x68BC -#define CTLANADRVPUCTL 0x68C8 -#define CTLANADRVPDCTL 0x68CC -#define CTLANADLYPUCTL 0x68D0 -#define CTLANADLYPDCTL 0x68D4 -#define CHNLBUFSTATIC 0x68F0 -#define COMPOBSCNTRL 0x68F4 -#define COMPBUFFDBG0 0x68F8 -#define COMPBUFFDBG1 0x68FC +#define CLKANATCOPDCTL 0x689c +#define DQSANAODTPUCTL 0x68a0 +#define DQSANAODTPDCTL 0x68a4 +#define DQSANADRVPUCTL 0x68a8 +#define DQSANADRVPDCTL 0x68ac +#define DQSANADLYPUCTL 0x68b0 +#define DQSANADLYPDCTL 0x68b4 +#define DQSANATCOPUCTL 0x68b8 +#define DQSANATCOPDCTL 0x68bc +#define CTLANADRVPUCTL 0x68c8 +#define CTLANADRVPDCTL 0x68cc +#define CTLANADLYPUCTL 0x68d0 +#define CTLANADLYPDCTL 0x68d4 +#define CHNLBUFSTATIC 0x68f0 +#define COMPOBSCNTRL 0x68f4 +#define COMPBUFFDBG0 0x68f8 +#define COMPBUFFDBG1 0x68fc #define CFGMISCCH0 0x6900 #define COMPEN0CH0 0x6904 #define COMPEN1CH0 0x6908 -#define COMPEN2CH0 0x690C +#define COMPEN2CH0 0x690c #define STATLEGEN0CH0 0x6910 #define STATLEGEN1CH0 0x6914 #define DQVREFCH0 0x6918 -#define CMDVREFCH0 0x691C +#define CMDVREFCH0 0x691c #define CLKVREFCH0 0x6920 #define DQSVREFCH0 0x6924 #define CTLVREFCH0 0x6928 -#define TCOVREFCH0 0x692C +#define TCOVREFCH0 0x692c #define DLYSELCH0 0x6930 #define TCODRAMBUFODTCH0 0x6934 #define CCBUFODTCH0 0x6938 -#define RXOFFSETCH0 0x693C +#define RXOFFSETCH0 0x693c #define DQODTPUCTLCH0 0x6940 #define DQODTPDCTLCH0 0x6944 #define DQDRVPUCTLCH0 0x6948 -#define DQDRVPDCTLCH0 0x694C +#define DQDRVPDCTLCH0 0x694c #define DQDLYPUCTLCH0 0x6950 #define DQDLYPDCTLCH0 0x6954 #define DQTCOPUCTLCH0 0x6958 -#define DQTCOPDCTLCH0 0x695C +#define DQTCOPDCTLCH0 0x695c #define CMDDRVPUCTLCH0 0x6968 -#define CMDDRVPDCTLCH0 0x696C +#define CMDDRVPDCTLCH0 0x696c #define CMDDLYPUCTLCH0 0x6970 #define CMDDLYPDCTLCH0 0x6974 #define CLKODTPUCTLCH0 0x6980 #define CLKODTPDCTLCH0 0x6984 #define CLKDRVPUCTLCH0 0x6988 -#define CLKDRVPDCTLCH0 0x698C +#define CLKDRVPDCTLCH0 0x698c #define CLKDLYPUCTLCH0 0x6990 #define CLKDLYPDCTLCH0 0x6994 #define CLKTCOPUCTLCH0 0x6998 -#define CLKTCOPDCTLCH0 0x699C -#define DQSODTPUCTLCH0 0x69A0 -#define DQSODTPDCTLCH0 0x69A4 -#define DQSDRVPUCTLCH0 0x69A8 -#define DQSDRVPDCTLCH0 0x69AC -#define DQSDLYPUCTLCH0 0x69B0 -#define DQSDLYPDCTLCH0 0x69B4 -#define DQSTCOPUCTLCH0 0x69B8 -#define DQSTCOPDCTLCH0 0x69BC -#define CTLDRVPUCTLCH0 0x69C8 -#define CTLDRVPDCTLCH0 0x69CC -#define CTLDLYPUCTLCH0 0x69D0 -#define CTLDLYPDCTLCH0 0x69D4 -#define FNLUPDTCTLCH0 0x69F0 +#define CLKTCOPDCTLCH0 0x699c +#define DQSODTPUCTLCH0 0x69a0 +#define DQSODTPDCTLCH0 0x69a4 +#define DQSDRVPUCTLCH0 0x69a8 +#define DQSDRVPDCTLCH0 0x69ac +#define DQSDLYPUCTLCH0 0x69b0 +#define DQSDLYPDCTLCH0 0x69b4 +#define DQSTCOPUCTLCH0 0x69b8 +#define DQSTCOPDCTLCH0 0x69bc +#define CTLDRVPUCTLCH0 0x69c8 +#define CTLDRVPDCTLCH0 0x69cc +#define CTLDLYPUCTLCH0 0x69d0 +#define CTLDLYPDCTLCH0 0x69d4 +#define FNLUPDTCTLCH0 0x69f0 /* PLL */ #define MPLLCTRL0 0x7800 @@ -332,17 +419,17 @@ #define MPLLDFT 0x7828 #define MPLLMON0CTL 0x7830 #define MPLLMON1CTL 0x7838 -#define MPLLMON2CTL 0x783C +#define MPLLMON2CTL 0x783c #define SFRTRIM 0x7850 #define MPLLDFTOUT0 0x7858 -#define MPLLDFTOUT1 0x785C +#define MPLLDFTOUT1 0x785c #define MASTERRSTN 0x7880 #define PLLLOCKDEL 0x7884 #define SFRDEL 0x7888 -#define CRUVISALANECR0 0x78F0 -#define CRUVISALANECR1 0x78F4 -#define CRUVISACONTROLCR 0x78F8 -#define IOSFVISALANECR0 0x78FC +#define CRUVISALANECR0 0x78f0 +#define CRUVISALANECR1 0x78f4 +#define CRUVISACONTROLCR 0x78f8 +#define IOSFVISALANECR0 0x78fc #define IOSFVISALANECR1 0x7900 #define IOSFVISACONTROLCR 0x7904 @@ -350,7 +437,7 @@ /* DRAM Specific Message Bus OpCodes */ #define MSG_OP_DRAM_INIT 0x68 -#define MSG_OP_DRAM_WAKE 0xCA +#define MSG_OP_DRAM_WAKE 0xca #define SAMPLE_SIZE 6 @@ -377,9 +464,9 @@ /* offset into "vref_codes[]" for minimum allowed VREF setting */ #define VREF_MIN 0x00 /* offset into "vref_codes[]" for maximum allowed VREF setting */ -#define VREF_MAX 0x3F +#define VREF_MAX 0x3f #define RDQS_MIN 0x00 /* minimum RDQS delay value */ -#define RDQS_MAX 0x3F /* maximum RDQS delay value */ +#define RDQS_MAX 0x3f /* maximum RDQS delay value */ /* how many WDQ codes to jump while margining */ #define WDQ_STEP 1 diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index f51f1121d0..2e5f9da756 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -11,7 +11,6 @@ */ #include <config.h> -#include <version.h> #include <asm/global_data.h> #include <asm/post.h> #include <asm/processor.h> diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h index ff15828a71..3a891ba627 100644 --- a/arch/x86/include/asm/config.h +++ b/arch/x86/include/asm/config.h @@ -7,7 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH |