diff options
| author | Dave Liu <daveliu@freescale.com> | 2009-11-17 20:49:05 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-25 22:14:39 -0600 |
| commit | 0fd2fa6cce6eb91271ebf9733878d0f1fcbc9b32 (patch) | |
| tree | d1bcb623fa9b0e461630eb60d6a5686a00b711ac /cpu | |
| parent | c95d541e4b46cb3ba19bf35e34b1dc3ca32f7b4b (diff) | |
Fix the local bus divider mapping
The real clock divider is 4 times of the bits LCRR[CLKDIV],
according the latest RevF RM.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc85xx/speed.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 9193992888..268edbc5b7 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -170,7 +170,12 @@ void get_sys_info (sys_info_t * sysInfo) } #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { -#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ +#if defined(CONFIG_FSL_CORENET) + /* If this is corenet based SoC, bit-representation + * for four times the clock divider values. + */ + lcrr_div *= 4; +#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \ !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560) /* * Yes, the entire PQ38 family use the same |