diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2015-06-18 09:06:34 +0200 |
|---|---|---|
| committer | Klaus Goger <klaus.goger@theobroma-systems.com> | 2015-07-30 18:44:06 +0200 |
| commit | dd84fb72199bc896ad491808255248fb01fbf271 (patch) | |
| tree | c5da49b074b5b01bcdab1c1f1e646e6d509fadf0 | |
| parent | 565623e22caab4111c223ba609b79a7b2a9e1f39 (diff) | |
ARM: sun6i: Enable sigma-delta on DDR-PLL5
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun6i.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c index 5dbbf6186f..b0b299ed41 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -33,7 +33,13 @@ static void mctl_sys_init(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int dram_clk_div = 2; - clock_set_pll5(DRAM_CLK * dram_clk_div, false); + clock_set_pll5(DRAM_CLK * dram_clk_div, true); + + /* TODO: investigate whether the increased mdelay is related to enabling + * sigma-delta above. If so, we might as well increase the value + * in the PLL lock-time register. + */ + mdelay(20); clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST | |