diff options
author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2015-06-18 00:40:43 +0200 |
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committer | Klaus Goger <klaus.goger@theobroma-systems.com> | 2015-07-30 18:44:06 +0200 |
commit | c4861d5c228f4ee0e3e26c20c45ad40bfc6f855e (patch) | |
tree | a5d6033a9f075aec8444d0b0edce513588628237 | |
parent | 617a6ea60b3d483bf2d151082bc34cc88d77a742 (diff) |
sun6i: Improve selection of 'k' and 'm' for PLL5
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 709178bf17..67fe605d5d 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -174,18 +174,23 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) { struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - const int max_n = 32; - int k = 1, m = 2; + int k = 3, m = 4; if (sigma_delta_enable) writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); /* PLL5 rate = 24000000 * n * k / m */ - if (clk > 24000000 * k * max_n / m) { - m = 1; - if (clk > 24000000 * k * max_n / m) - k = 2; + if (clk > 1152000000) { + k = 4; + m = 2; + } else if (clk > 768000000) { + k = 3; + m = 2; + } else if (clk > 576000000) { + k = 2; + m = 2; } + writel(CCM_PLL5_CTRL_EN | (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | CCM_PLL5_CTRL_UPD | |