diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2015-01-06 15:47:18 +0100 |
|---|---|---|
| committer | Klaus Goger <klaus.goger@theobroma-systems.com> | 2015-07-30 18:44:04 +0200 |
| commit | a58eb20fb80f478038243e9e0f30f6984725e265 (patch) | |
| tree | 411d5a9f1c57f8255bd26a0f14e65b07be7d5124 | |
| parent | 49b7887bbef2bb243229b04c0422465a1ae7f8a8 (diff) | |
sun6i: Sync PLL1 multipliers/dividers with Boot1
This change syncs up the multipliers and dividers used to initialize
PLL1 (i.e. the fast clock driving the ARM cores) with the values used
in Allwinner's Boot1 on sun6i.
More specifically, the following settings are now used:
* up to 768MHz: mul=2, div=2 (was: mul=1, div=1)
* up to 1152MHz: mul=3, div=2 (unchanged)
* above 1152MHz: mul=4, div=2 (was: mul=2, div=1)
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index cfb32b4323..2986539625 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -102,11 +102,12 @@ void clock_set_pll1(unsigned int clk) struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int p = 0; - int k = 1; - int m = 1; + int k = 2; + int m = 2; if (clk > 1152000000) { - k = 2; + k = 4; + m = 2; } else if (clk > 768000000) { k = 3; m = 2; |