sun6i: Handle PLL5 UPD/LOCK bits per specification

PLL5-DDR is different from other PLLs by having an additional
auto-clearing UPD bit (that validates the PLL and needs to be set
after any change to the PLL5 configuration).

The manual requires the following steps to set up PLL5:
 1. Set up operational parameters.
 2. Enabled the PLL (PLL5_ENABLE bit).
 3. Set the UPD-bit (variously referred to as bit 20 or SDRPLL_UPD
    in the manual) and wait for it to clear.
 4. Wait for the LOCK bit to assert.

1 files changed, 7 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 3a6e56e300..986c4905fa 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -192,6 +192,13 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 	       CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
 	       CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
 
+	setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_UPD);
+
+       /* On PLL5, the update needs first to take effect (i.e. CCM_PLL5_CTRL_UPD
+	* must auto-clear... and only then we can wait for the PLL to lock.  */
+	while (readl(&ccm->pll5_cfg) & CCM_PLL5_CTRL_UPD)
+	  /* spin */ ;
+
 	wait_for_pll_lock(&ccm->pll5_cfg);
 }