summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/am35xx-clocks.dtsi
blob: df489d310b50aa0ad01f7750cb6fb17ea36da540 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
/*
 * Device Tree Source for OMAP3 clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
&scrm_clocks {
	emac_ick: emac_ick {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x059c>;
		ti,bit-shift = <1>;
	};

	emac_fck: emac_fck {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&rmii_ck>;
		reg = <0x059c>;
		ti,bit-shift = <9>;
	};

	vpfe_ick: vpfe_ick {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x059c>;
		ti,bit-shift = <2>;
	};

	vpfe_fck: vpfe_fck {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&pclk_ck>;
		reg = <0x059c>;
		ti,bit-shift = <10>;
	};

	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x059c>;
		ti,bit-shift = <0>;
	};

	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_ck>;
		reg = <0x059c>;
		ti,bit-shift = <8>;
	};

	hecc_ck: hecc_ck {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&sys_ck>;
		reg = <0x059c>;
		ti,bit-shift = <3>;
	};
};
&cm_clocks {
	ipss_ick: ipss_ick {
		#clock-cells = <0>;
		compatible = "ti,am35xx-interface-clock";
		clocks = <&core_l3_ick>;
		reg = <0x0a10>;
		ti,bit-shift = <4>;
	};

	rmii_ck: rmii_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
	};

	pclk_ck: pclk_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
	};

	uart4_ick_am35xx: uart4_ick_am35xx {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&core_l4_ick>;
		reg = <0x0a10>;
		ti,bit-shift = <23>;
	};

	uart4_fck_am35xx: uart4_fck_am35xx {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&core_48m_fck>;
		reg = <0x0a00>;
		ti,bit-shift = <23>;
	};
};

&cm_clockdomains {
	core_l3_clkdm: core_l3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
			 <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
			 <&hecc_ck>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
			 <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
	};
};