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path: root/drivers/staging/sm750fb/ddk750_display.c
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Diffstat (limited to 'drivers/staging/sm750fb/ddk750_display.c')
-rw-r--r--drivers/staging/sm750fb/ddk750_display.c200
1 files changed, 68 insertions, 132 deletions
diff --git a/drivers/staging/sm750fb/ddk750_display.c b/drivers/staging/sm750fb/ddk750_display.c
index 84f6e8b8c0e2..ca4973ee49e4 100644
--- a/drivers/staging/sm750fb/ddk750_display.c
+++ b/drivers/staging/sm750fb/ddk750_display.c
@@ -9,111 +9,55 @@
static void setDisplayControl(int ctrl, int disp_state)
{
/* state != 0 means turn on both timing & plane en_bit */
- unsigned long ulDisplayCtrlReg, ulReservedBits;
- int cnt;
+ unsigned long reg, val, reserved;
+ int cnt = 0;
- cnt = 0;
-
- /* Set the primary display control */
if (!ctrl) {
- ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL);
- /* Turn on/off the Panel display control */
- if (disp_state) {
- /* Timing should be enabled first before enabling the plane
- * because changing at the same time does not guarantee that
- * the plane will also enabled or disabled.
- */
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- PANEL_DISPLAY_CTRL, TIMING, ENABLE);
- POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
-
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- PANEL_DISPLAY_CTRL, PLANE, ENABLE);
-
- /* Added some masks to mask out the reserved bits.
- * Sometimes, the reserved bits are set/reset randomly when
- * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
- * reserved bits are needed to be masked out.
- */
- ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
- FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
- FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE);
-
- /* Somehow the register value on the plane is not set
- * until a few delay. Need to write
- * and read it a couple times
- */
- do {
- cnt++;
- POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
- } while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) !=
- (ulDisplayCtrlReg & ~ulReservedBits));
- printk("Set Panel Plane enbit:after tried %d times\n", cnt);
- } else {
- /* When turning off, there is no rule on the programming
- * sequence since whenever the clock is off, then it does not
- * matter whether the plane is enabled or disabled.
- * Note: Modifying the plane bit will take effect on the
- * next vertical sync. Need to find out if it is necessary to
- * wait for 1 vsync before modifying the timing enable bit.
- * */
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- PANEL_DISPLAY_CTRL, PLANE, DISABLE);
- POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
-
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- PANEL_DISPLAY_CTRL, TIMING, DISABLE);
- POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
- }
-
+ reg = PANEL_DISPLAY_CTRL;
+ reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK;
} else {
- /* Set the secondary display control */
- ulDisplayCtrlReg = PEEK32(CRT_DISPLAY_CTRL);
-
- if (disp_state) {
- /* Timing should be enabled first before enabling the plane because changing at the
- same time does not guarantee that the plane will also enabled or disabled.
- */
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- CRT_DISPLAY_CTRL, TIMING, ENABLE);
- POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
-
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- CRT_DISPLAY_CTRL, PLANE, ENABLE);
-
- /* Added some masks to mask out the reserved bits.
- * Sometimes, the reserved bits are set/reset randomly when
- * writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
- * reserved bits are needed to be masked out.
- */
-
- ulReservedBits = FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
- FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
- FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) |
- FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE);
+ reg = CRT_DISPLAY_CTRL;
+ reserved = CRT_DISPLAY_CTRL_RESERVED_MASK;
+ }
- do {
- cnt++;
- POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
- } while ((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) !=
- (ulDisplayCtrlReg & ~ulReservedBits));
- printk("Set Crt Plane enbit:after tried %d times\n", cnt);
- } else {
- /* When turning off, there is no rule on the programming
- * sequence since whenever the clock is off, then it does not
- * matter whether the plane is enabled or disabled.
- * Note: Modifying the plane bit will take effect on the next
- * vertical sync. Need to find out if it is necessary to
- * wait for 1 vsync before modifying the timing enable bit.
- */
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- CRT_DISPLAY_CTRL, PLANE, DISABLE);
- POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
-
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- CRT_DISPLAY_CTRL, TIMING, DISABLE);
- POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
- }
+ val = PEEK32(reg);
+ if (disp_state) {
+ /*
+ * Timing should be enabled first before enabling the
+ * plane because changing at the same time does not
+ * guarantee that the plane will also enabled or
+ * disabled.
+ */
+ val |= DISPLAY_CTRL_TIMING;
+ POKE32(reg, val);
+
+ val |= DISPLAY_CTRL_PLANE;
+
+ /*
+ * Somehow the register value on the plane is not set
+ * until a few delay. Need to write and read it a
+ * couple times
+ */
+ do {
+ cnt++;
+ POKE32(reg, val);
+ } while ((PEEK32(reg) & ~reserved) != (val & ~reserved));
+ pr_debug("Set Plane enbit:after tried %d times\n", cnt);
+ } else {
+ /*
+ * When turning off, there is no rule on the
+ * programming sequence since whenever the clock is
+ * off, then it does not matter whether the plane is
+ * enabled or disabled. Note: Modifying the plane bit
+ * will take effect on the next vertical sync. Need to
+ * find out if it is necessary to wait for 1 vsync
+ * before modifying the timing enable bit.
+ */
+ val &= ~DISPLAY_CTRL_PLANE;
+ POKE32(reg, val);
+
+ val &= ~DISPLAY_CTRL_TIMING;
+ POKE32(reg, val);
}
}
@@ -126,54 +70,42 @@ static void waitNextVerticalSync(int ctrl, int delay)
/* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */
- if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
- PANEL_PLL_CTRL_POWER_OFF) ||
- (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
- PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
+ if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
+ !(PEEK32(PANEL_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) {
return;
}
while (delay-- > 0) {
/* Wait for end of vsync. */
do {
- status = FIELD_GET(PEEK32(SYSTEM_CTRL),
- SYSTEM_CTRL,
- PANEL_VSYNC);
- } while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
+ status = PEEK32(SYSTEM_CTRL);
+ } while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
/* Wait for start of vsync. */
do {
- status = FIELD_GET(PEEK32(SYSTEM_CTRL),
- SYSTEM_CTRL,
- PANEL_VSYNC);
- } while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE);
+ status = PEEK32(SYSTEM_CTRL);
+ } while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
}
} else {
/* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */
- if ((FIELD_GET(PEEK32(CRT_PLL_CTRL), CRT_PLL_CTRL, POWER) ==
- CRT_PLL_CTRL_POWER_OFF) ||
- (FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) ==
- CRT_DISPLAY_CTRL_TIMING_DISABLE)) {
+ if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
+ !(PEEK32(CRT_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) {
return;
}
while (delay-- > 0) {
/* Wait for end of vsync. */
do {
- status = FIELD_GET(PEEK32(SYSTEM_CTRL),
- SYSTEM_CTRL,
- CRT_VSYNC);
- } while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE);
+ status = PEEK32(SYSTEM_CTRL);
+ } while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
/* Wait for start of vsync. */
do {
- status = FIELD_GET(PEEK32(SYSTEM_CTRL),
- SYSTEM_CTRL,
- CRT_VSYNC);
- } while (status == SYSTEM_CTRL_CRT_VSYNC_INACTIVE);
+ status = PEEK32(SYSTEM_CTRL);
+ } while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
}
}
}
@@ -184,22 +116,22 @@ static void swPanelPowerSequence(int disp, int delay)
/* disp should be 1 to open sequence */
reg = PEEK32(PANEL_DISPLAY_CTRL);
- reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp);
+ reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
POKE32(PANEL_DISPLAY_CTRL, reg);
primaryWaitVerticalSync(delay);
reg = PEEK32(PANEL_DISPLAY_CTRL);
- reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, DATA, disp);
+ reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0);
POKE32(PANEL_DISPLAY_CTRL, reg);
primaryWaitVerticalSync(delay);
reg = PEEK32(PANEL_DISPLAY_CTRL);
- reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, VBIASEN, disp);
+ reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0);
POKE32(PANEL_DISPLAY_CTRL, reg);
primaryWaitVerticalSync(delay);
reg = PEEK32(PANEL_DISPLAY_CTRL);
- reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp);
+ reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
POKE32(PANEL_DISPLAY_CTRL, reg);
primaryWaitVerticalSync(delay);
@@ -212,16 +144,20 @@ void ddk750_setLogicalDispOut(disp_output_t output)
if (output & PNL_2_USAGE) {
/* set panel path controller select */
reg = PEEK32(PANEL_DISPLAY_CTRL);
- reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, SELECT, (output & PNL_2_MASK)>>PNL_2_OFFSET);
+ reg &= ~PANEL_DISPLAY_CTRL_SELECT_MASK;
+ reg |= (((output & PNL_2_MASK) >> PNL_2_OFFSET) <<
+ PANEL_DISPLAY_CTRL_SELECT_SHIFT);
POKE32(PANEL_DISPLAY_CTRL, reg);
}
if (output & CRT_2_USAGE) {
/* set crt path controller select */
reg = PEEK32(CRT_DISPLAY_CTRL);
- reg = FIELD_VALUE(reg, CRT_DISPLAY_CTRL, SELECT, (output & CRT_2_MASK)>>CRT_2_OFFSET);
+ reg &= ~CRT_DISPLAY_CTRL_SELECT_MASK;
+ reg |= (((output & CRT_2_MASK) >> CRT_2_OFFSET) <<
+ CRT_DISPLAY_CTRL_SELECT_SHIFT);
/*se blank off */
- reg = FIELD_SET(reg, CRT_DISPLAY_CTRL, BLANK, OFF);
+ reg &= ~CRT_DISPLAY_CTRL_BLANK;
POKE32(CRT_DISPLAY_CTRL, reg);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 08:41:20 +0000