Clk: sunxi: Adding support for GPU clocks and PLL8/9.

This patch adds support for the GPU clocks on sun6i a31.
This is a typical clock path, which can be realized with this patch:

 * PLL8 -> GPU_HYD
        -> GPU_MEM
 * PLL9 -> GPU_CORE
 * AHB1 -> AHB1_GPU

Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>

2 files changed, 53 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/sun6i-a31-pangolin.dts b/arch/arm/boot/dts/sun6i-a31-pangolin.dts
index 7de0e70e16c3..9d7dbb40b022 100644
--- a/arch/arm/boot/dts/sun6i-a31-pangolin.dts
+++ b/arch/arm/boot/dts/sun6i-a31-pangolin.dts
@@ -137,6 +137,10 @@
 	status = "okay";
 };
 
+&gpu {
+	status = "okay";
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_pangolin>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 9ea8c31b1352..cf7f5a31a41b 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -187,6 +187,7 @@
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
 		};
 
 		osc32k: clk@0 {
@@ -212,6 +213,22 @@
 			clock-output-names = "pll6", "pll6x2";
 		};
 
+		pll8: clk@01c20038 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun6i-a31-pll8-clk";
+			reg = <0x01c20038 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll8";
+		};
+
+		pll9: clk@01c20044 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun6i-a31-pll9-clk";
+			reg = <0x01c20044 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll9";
+		};
+
 		cpu: cpu@01c20050 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-cpu-clk";
@@ -392,6 +409,30 @@
 					     "usb_ohci2";
 		};
 
+		gpucore_clk: clk@01c201a0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun6i-a31-gpu-clk";
+			reg = <0x01c201a0 0x4>;
+			clocks = <&pll9>;
+			clock-output-names = "gpucore";
+		};
+
+		gpumem_clk: clk@01c201a4 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun6i-a31-gpu-clk";
+			reg = <0x01c201a4 0x4>;
+			clocks = <&pll8>;
+			clock-output-names = "gpumem";
+		};
+
+		gpuhyd_clk: clk@01c201a8 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun6i-a31-gpu-clk";
+			reg = <0x01c201a8 0x4>;
+			clocks = <&pll8>;
+			clock-output-names = "gpuhyd";
+		};
+
 		/*
 		 * The following two are dummy clocks, placeholders used in the gmac_tx
 		 * clock. The gmac driver will choose one parent depending on the PHY
@@ -928,6 +969,14 @@
 			status = "disabled";
 		};
 
+		gpu: gpu@01c40000 {
+			clocks = <&ahb1_gates 52>, <&gpucore_clk>, <&gpumem_clk>, <&gpuhyd_clk>;
+			clock-names = "ahb", "gpucore", "gpumem", "gpuhyd";
+			resets = <&ahb1_rst 52>;
+			reset-names = "ahb";
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@01c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,