diff options
| author | Christoph Muellner <christoph.muellner@theobroma-systems.com> | 2015-07-17 16:50:58 +0200 |
|---|---|---|
| committer | Klaus Goger <klaus.goger@theobroma-systems.com> | 2015-07-30 18:53:04 +0200 |
| commit | 9eda7e7de6bf90c67502acf04bbdc7d074781b9d (patch) | |
| tree | c55bee44cb4f5d47a8625421ce9eb0327af3b55c | |
| parent | 8408b6ce97d05b928d65029e429c8da3ae775010 (diff) | |
clk: sunxi: Address sun6i PLL1 stability issues.
Tests on several Allwinner A31 SoCs showed that PLL1
has problems when using low values for M in combination
with high target frequencies.
This patch addresses this issue by limiting M, such that
it does not divide values higher than 2.6 GHz.
Reported-by: Philip Tomsich <philip.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
| -rw-r--r-- | drivers/clk/sunxi/clk-sunxi.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 692680d1b716..8135e311d38d 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -305,7 +305,7 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, const u8 f0[11] = {3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}; /* 2^3 * 3^1 */ const u8 N_max = 32; /* 5 bits */ const u8 K_max = 4; /* 2 bits */ - const u8 M_max = 4; /* 2 bits */ + u8 M_max = 4; /* 2 bits */ u8 N = 1, K = 1, M = 1; /* multiplicators (e.g. N = n+1) */ u32 freq_mhz, tmp; u8 success; @@ -314,6 +314,18 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, freq_mhz = *freq / 1000000; + /* Limit (24 MHz * (n+1) * (k+1)) to be less than 2.6 GHz + * This is caused by stability issues observed. + */ + if (freq_mhz <= 400) + M_max = 4; + else if (freq_mhz <= 800) + M_max = 3; + else if (freq_mhz <= 1200) + M_max = 2; + else + M_max = 1; + /* minimum possible frequency is 6 */ if (freq_mhz<6) freq_mhz = 6; |