diff options
author | Octav Zlatior <octav.zlatior@theobroma-systems.com> | 2015-06-08 15:55:39 +0200 |
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committer | Klaus Goger <klaus.goger@theobroma-systems.com> | 2015-07-30 18:53:03 +0200 |
commit | 9de13853d408d7130fcebb3d7aea6e6474cf34da (patch) | |
tree | 3ddf20cd4ef6d7500f5f1364c7e79bddffda33f6 | |
parent | 52d098616088c46f7b9a23c8f55502bd93bc94ec (diff) |
clk: sunxi: removes pll stability tweaks
The pll stability tweaks are no longer necessary, since the cpu
clock uses the transition parent while the pll changes the frequency
Signed-off-by: Octav Zlatior <octav.zlatior@theobroma-systems.com>
-rw-r--r-- | drivers/clk/sunxi/clk-sunxi.c | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 1f02b028db48..692680d1b716 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -390,62 +390,6 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, return; } - /* some tweaks to improve pll stability */ - /* The pll can be quite tricky with tranzitions; these tweaks are based on - * empirical observations on the behaviour of the pll */ - /* M cannot be too low */ - switch (M) { - case 1: { - u8 factor = 1; - if (N*4 <= N_max) - factor = 4; - else if (N*3 <= N_max) - factor = 2; - else if (N*2 <= N_max) - factor = 2; - M *= factor; - N *= factor; - break; - } - case 2: - if (N*2 <= N_max) { - M *= 2; - N *= 2; - } - break; - } - /* K cannot be too low either */ - switch (K) { - case 1: { - u8 factor = 1; - if (N%4 == 0) - factor = 4; - else if (N%3 == 0) - factor = 3; - else if (N%2 == 0) - factor = 2; - K *= factor; - N /= factor; - break; - } - case 2: - if (N%2 == 0) { - K *= 2; - N /= 2; - } - break; - } - /* 3 is the best value ever! */ - if (K==M && K!=3) - K = M = 3; - /* 4 is better than 2, 2 is better than 1 */ - else if (M<3 && K<3) { - M *= 2; - K *= 2; - } - - *freq = (parent_rate * N * K) / M; - /* finally, setting the register values based on N, K and M */ if (n != NULL) { *n = N-1; |