diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2015-03-25 01:22:08 +0800 |
|---|---|---|
| committer | Klaus Goger <klaus.goger@theobroma-systems.com> | 2015-07-30 18:52:52 +0200 |
| commit | 30919f3ac3d21e2c3a90fe807613b88906d45ecc (patch) | |
| tree | dea377eb691d4069d4693f800a9e80e7fa576353 | |
| parent | c3e4856ef80b036a0e0d869f66aa53e9a64e7306 (diff) | |
clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6
The pll6 has a /4 output that is used as an input to the ahb mux clock.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
| -rw-r--r-- | drivers/clk/sunxi/clk-sunxi.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index 7c5b9834f7a7..95859355c880 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -1173,11 +1173,12 @@ static const struct divs_data pll5_divs_data __initconst = { static const struct divs_data pll6_divs_data __initconst = { .factors = &sun4i_pll6_data, - .ndivs = 3, + .ndivs = 4, .div = { { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ { .fixed = 2 }, /* P, other */ { .self = 1 }, /* base factor clock, 2x */ + { .fixed = 4 }, /* pll6 / 4, used as ahb input */ } }; |