From 0eac5b57a2455bb44f10279c211743102dae7888 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 2 Apr 2018 09:59:00 +0800 Subject: core: arm: imx: a9: tune ACTLR Tune ACTLR. To SLL, the value is 0xE at runtime. To others, the value should be 0x4F at runtime. Bit3 will be enabled when enable L2. The SMP bit for i.MX6SLL needs to be make ldrex/strex instruction work properly. Signed-off-by: Peng Fan Acked-by: Jens Wiklander Acked-by: Rouven Czerwinski --- core/arch/arm/plat-imx/a9_plat_init.S | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'core') diff --git a/core/arch/arm/plat-imx/a9_plat_init.S b/core/arch/arm/plat-imx/a9_plat_init.S index dee142f0..8a11198f 100644 --- a/core/arch/arm/plat-imx/a9_plat_init.S +++ b/core/arch/arm/plat-imx/a9_plat_init.S @@ -74,10 +74,12 @@ UNWIND( .fnstart) * SCTLR = 0x00004000 * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin) * - * ACTRL = 0x00000041 - * - core always in full SMP (FW bit0=1, SMP bit6=1) + * ACTRL = 0x000000[46(i.MX6SLL),47] + * - core always in full SMP (FW bit0=[0(i.MX6SLL),1], SMP bit6=1) * - L2 write full line of zero disabled (bit3=0) * (keep WFLZ low. Will be set once outer L2 is ready) + * - L1 Prefetch enable (bit2=1) + * - L2 Prefetch hint enable (bit1=1) * * NSACR = 0x00020C00 * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) @@ -91,7 +93,11 @@ UNWIND( .fnstart) mov_imm r0, 0x00004000 write_sctlr r0 - mov_imm r0, 0x00000041 +#ifdef CFG_MX6SLL + mov_imm r0, 0x00000046 +#else + mov_imm r0, 0x00000047 +#endif write_actlr r0 mov_imm r0, 0x00020C00 -- cgit v1.2.3