From 42615b81f3f7b3bebd6a8e2b5e325ac477bc4e4b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 6 Dec 2018 14:06:24 +0800 Subject: plat-imx: add i.MX8MQ/MM EVK support Add i.MX8MQ/MM EVK support. i.MX8M family use Cortex-A53 as the CPU core, the i.MX8MQ EVK has 3GB DRAM memory, and i.MX8MM EVK has 2GB DRAM memory. Signed-off-by: Peng Fan Acked-by: Jerome Forissier --- core/arch/arm/plat-imx/conf.mk | 58 ++++++++++++++++++++++++++++++++++----- core/arch/arm/plat-imx/imx-regs.h | 10 +++++++ core/arch/arm/plat-imx/main.c | 24 +++++++++++++++- core/arch/arm/plat-imx/sub.mk | 4 +-- 4 files changed, 86 insertions(+), 10 deletions(-) (limited to 'core/arch/arm/plat-imx') diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk index 239e647c..1b7178ac 100644 --- a/core/arch/arm/plat-imx/conf.mk +++ b/core/arch/arm/plat-imx/conf.mk @@ -31,6 +31,12 @@ mx7-flavorlist = \ mx7swarp7 \ mx7dclsom \ +imx8mq-flavorlist = \ + imx8mqevk + +imx8mm-flavorlist = \ + imx8mmevk + ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist))) $(call force,CFG_MX6,y) $(call force,CFG_MX6UL,y) @@ -65,6 +71,18 @@ else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7-flavorlist))) $(call force,CFG_MX7,y) CFG_TEE_CORE_NB_CORE ?= 2 include core/arch/arm/cpu/cortex-a7.mk +else ifneq (,$(filter $(PLATFORM_FLAVOR),$(imx8mq-flavorlist))) +$(call force,CFG_IMX8MQ,y) +$(call force,CFG_ARM64_core,y) +CFG_IMX_UART ?= y +CFG_DRAM_BASE ?= 0x40000000 +CFG_TEE_CORE_NB_CORE ?= 4 +else ifneq (,$(filter $(PLATFORM_FLAVOR),$(imx8mm-flavorlist))) +$(call force,CFG_IMX8MM,y) +$(call force,CFG_ARM64_core,y) +CFG_IMX_UART ?= y +CFG_DRAM_BASE ?= 0x40000000 +CFG_TEE_CORE_NB_CORE ?= 4 else $(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)") endif @@ -124,6 +142,16 @@ CFG_DDR_SIZE ?= 0x20000000 CFG_NS_ENTRY_ADDR ?= 0x80800000 endif +ifneq (,$(filter $(PLATFORM_FLAVOR),imx8mqevk)) +CFG_DDR_SIZE ?= 0xc0000000 +CFG_UART_BASE ?= UART1_BASE +endif + +ifneq (,$(filter $(PLATFORM_FLAVOR),imx8mmevk)) +CFG_DDR_SIZE ?= 0x80000000 +CFG_UART_BASE ?= UART2_BASE +endif + # i.MX6 Solo/SoloX/DualLite/Dual/Quad specific config ifeq ($(filter y, $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \ $(CFG_MX6SX)), y) @@ -157,18 +185,11 @@ $(call force,CFG_WITH_SOFTWARE_PRNG,y) CFG_BOOT_SYNC_CPU ?= n CFG_BOOT_SECONDARY_REQUEST ?= y -CFG_CRYPTO_SIZE_OPTIMIZATION ?= n CFG_DT ?= y CFG_PAGEABLE_ADDR ?= 0 CFG_PSCI_ARM32 ?= y CFG_SECURE_TIME_SOURCE_REE ?= y CFG_UART_BASE ?= UART1_BASE -CFG_WITH_STACK_CANARIES ?= y - -CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - 0x02000000 + $(CFG_DDR_SIZE)) -CFG_TZDRAM_SIZE ?= 0x01e00000 -CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) -CFG_SHMEM_SIZE ?= 0x00200000 ta-targets = ta_arm32 endif @@ -178,4 +199,27 @@ CFG_HWSUPP_MEM_PERM_WXN = n CFG_IMX_WDOG ?= y endif +ifeq ($(CFG_ARM64_core),y) +# arm-v8 platforms +include core/arch/arm/cpu/cortex-armv8-0.mk +$(call force,CFG_ARM_GICV3,y) +$(call force,CFG_GENERIC_BOOT,y) +$(call force,CFG_GIC,y) +$(call force,CFG_WITH_LPAE,y) +$(call force,CFG_WITH_ARM_TRUSTED_FW,y) +$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) + +CFG_CRYPTO_WITH_CE ?= y +CFG_PM_STUBS ?= y + +ta-targets = ta_arm64 +endif + +CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - 0x02000000 + $(CFG_DDR_SIZE)) +CFG_TZDRAM_SIZE ?= 0x01e00000 +CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) +CFG_SHMEM_SIZE ?= 0x00200000 + +CFG_CRYPTO_SIZE_OPTIMIZATION ?= n +CFG_WITH_STACK_CANARIES ?= y CFG_MMAP_REGIONS ?= 24 diff --git a/core/arch/arm/plat-imx/imx-regs.h b/core/arch/arm/plat-imx/imx-regs.h index 242cfc94..5b8190c6 100644 --- a/core/arch/arm/plat-imx/imx-regs.h +++ b/core/arch/arm/plat-imx/imx-regs.h @@ -197,6 +197,16 @@ #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_OFFSET 26 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26) #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27) +#elif defined(CFG_IMX8MQ) || defined(CFG_IMX8MM) +#define GICD_BASE 0x38800000 +#define GICR_BASE 0x38880000 +#define UART1_BASE 0x30860000 +#define UART2_BASE 0x30890000 +#define UART3_BASE 0x30880000 +#define UART4_BASE 0x30A60000 +#define TZASC_BASE 0x32F80000 +#define CAAM_BASE 0x30900000 +#define ANATOP_BASE 0x30360000 #else #error "CFG_MX6/7 not defined" #endif diff --git a/core/arch/arm/plat-imx/main.c b/core/arch/arm/plat-imx/main.c index 9dd757cd..2b5adeb5 100644 --- a/core/arch/arm/plat-imx/main.c +++ b/core/arch/arm/plat-imx/main.c @@ -27,7 +27,7 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#include +#include #include #include #include @@ -52,12 +52,21 @@ static const struct thread_handlers handlers = { .std_smc = tee_entry_std, .fast_smc = tee_entry_fast, .nintr = main_fiq, +#if defined(CFG_WITH_ARM_TRUSTED_FW) + .cpu_on = cpu_on_handler, + .cpu_off = pm_do_nothing, + .cpu_suspend = pm_do_nothing, + .cpu_resume = pm_do_nothing, + .system_off = pm_do_nothing, + .system_reset = pm_do_nothing, +#else .cpu_on = pm_panic, .cpu_off = pm_panic, .cpu_suspend = pm_panic, .cpu_resume = pm_panic, .system_off = pm_panic, .system_reset = pm_panic, +#endif }; static struct imx_uart_data console_data; @@ -121,6 +130,18 @@ void console_init(void) void main_init_gic(void) { +#ifdef CFG_ARM_GICV3 + vaddr_t gicd_base; + + gicd_base = core_mmu_get_va(GICD_BASE, MEM_AREA_IO_SEC); + + if (!gicd_base) + panic(); + + /* Initialize GIC */ + gic_init(&gic_data, 0, gicd_base); + itr_init(&gic_data.chip); +#else vaddr_t gicc_base; vaddr_t gicd_base; @@ -133,6 +154,7 @@ void main_init_gic(void) /* Initialize GIC */ gic_init(&gic_data, gicc_base, gicd_base); itr_init(&gic_data.chip); +#endif } #if defined(CFG_MX6Q) || defined(CFG_MX6D) || defined(CFG_MX6DL) || \ diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk index cd9ccf29..fa463656 100644 --- a/core/arch/arm/plat-imx/sub.mk +++ b/core/arch/arm/plat-imx/sub.mk @@ -1,7 +1,7 @@ global-incdirs-y += . -srcs-y += main.c imx-common.c +srcs-y += main.c -srcs-$(CFG_MX6)$(CFG_MX7) += mmdc.c +srcs-$(CFG_MX6)$(CFG_MX7) += mmdc.c imx-common.c srcs-$(CFG_PL310) += imx_pl310.c ifeq ($(CFG_PSCI_ARM32),y) -- cgit v1.2.3