diff options
author | Sandeep Tripathy <sandeep.tripathy@broadcom.com> | 2019-04-02 15:30:13 +0530 |
---|---|---|
committer | Joakim Bech <joakim.bech@linaro.org> | 2019-04-23 15:17:08 +0700 |
commit | 7695df0549f966b3775d8b8dba8c4b190349c84f (patch) | |
tree | 0f4b55e2453b2851b3224bf4cd56fb4c4baa7197 /core | |
parent | f9044cdbc65b1d748f5267fc2083de773c06b17e (diff) |
plat-bcm: update platform configurations
-add more device ranges and definitions.
-fix dynamic shm api.
-cleanup plaform def.
-enable PL022 SPI, bcm HWRNG and bcm SOTP driver.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Diffstat (limited to 'core')
-rw-r--r-- | core/arch/arm/plat-bcm/conf.mk | 13 | ||||
-rw-r--r-- | core/arch/arm/plat-bcm/main.c | 14 | ||||
-rw-r--r-- | core/arch/arm/plat-bcm/platform_config.h | 38 |
3 files changed, 50 insertions, 15 deletions
diff --git a/core/arch/arm/plat-bcm/conf.mk b/core/arch/arm/plat-bcm/conf.mk index 53afba26..5c9bafa4 100644 --- a/core/arch/arm/plat-bcm/conf.mk +++ b/core/arch/arm/plat-bcm/conf.mk @@ -1,12 +1,12 @@ PLATFORM_FLAVOR ?= ns3 +include core/arch/arm/cpu/cortex-armv8-0.mk + $(call force,CFG_8250_UART,y) $(call force,CFG_GENERIC_BOOT,y) $(call force,CFG_TEE_CORE_DEBUG,n) $(call force,CFG_GIC,y) -ifeq ($(PLATFORM_FLAVOR),ns3) -platform-flavor-armv8 := 1 $(call force,CFG_WITH_LPAE,y) $(call force,CFG_ARM_GICV3,y) $(call force,CFG_CORE_CLUSTER_SHIFT,1) @@ -16,17 +16,18 @@ CFG_TZDRAM_SIZE ?= 0x01000000 # 16MB CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) - $(CFG_SHMEM_SIZE)) CFG_SHMEM_SIZE ?= 0x01000000 # 16MB CFG_TEE_RAM_VA_SIZE := 0x400000 # 4MB -endif -ifeq ($(platform-flavor-armv8),1) $(call force,CFG_WITH_ARM_TRUSTED_FW,y) $(call force,CFG_PM_STUBS,y) $(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) + +ifeq ($(PLATFORM_FLAVOR),ns3) +$(call force,CFG_PL022,y) +$(call force,CFG_BCM_HWRNG,y) +$(call force,CFG_BCM_SOTP,y) endif -ifeq ($(platform-flavor-armv8),1) ifeq ($(DEBUG),1) platform-cflags += -gdwarf-2 platform-aflags += -gdwarf-2 endif -endif diff --git a/core/arch/arm/plat-bcm/main.c b/core/arch/arm/plat-bcm/main.c index bdfca4fc..275361e4 100644 --- a/core/arch/arm/plat-bcm/main.c +++ b/core/arch/arm/plat-bcm/main.c @@ -39,8 +39,20 @@ register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE0_BASE, BCM_DEVICE0_SIZE); #ifdef BCM_DEVICE1_BASE register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE1_BASE, BCM_DEVICE1_SIZE); #endif +#ifdef BCM_DEVICE2_BASE +register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE2_BASE, BCM_DEVICE2_SIZE); +#endif +#ifdef BCM_DEVICE3_BASE +register_phys_mem_pgdir(MEM_AREA_IO_SEC, BCM_DEVICE3_BASE, BCM_DEVICE3_SIZE); +#endif #ifdef BCM_DRAM0_NS_BASE -register_dynamic_shm(MEM_AREA_RAM_NSEC, BCM_DRAM0_NS_BASE, BCM_DRAM0_NS_SIZE); +register_dynamic_shm(BCM_DRAM0_NS_BASE, BCM_DRAM0_NS_SIZE); +#endif +#ifdef BCM_DRAM1_NS_BASE +register_dynamic_shm(BCM_DRAM1_NS_BASE, BCM_DRAM1_NS_SIZE); +#endif +#ifdef BCM_DRAM2_NS_BASE +register_dynamic_shm(BCM_DRAM2_NS_BASE, BCM_DRAM2_NS_SIZE); #endif const struct thread_handlers *generic_boot_get_handlers(void) diff --git a/core/arch/arm/plat-bcm/platform_config.h b/core/arch/arm/plat-bcm/platform_config.h index 6a7e8d66..cec39842 100644 --- a/core/arch/arm/plat-bcm/platform_config.h +++ b/core/arch/arm/plat-bcm/platform_config.h @@ -8,22 +8,44 @@ #include <mm/generic_ram_layout.h> -#if defined(PLATFORM_FLAVOR_ns3) - #define STACK_ALIGNMENT 64 #define CONSOLE_UART_CLK_IN_HZ 25000000 #define CONSOLE_BAUDRATE 115200 #define CONSOLE_UART_BASE 0x68a10000 -#define BCM_DEVICE0_BASE CONSOLE_UART_BASE -#define BCM_DEVICE0_SIZE CORE_MMU_PGDIR_SIZE #define GICD_BASE 0x63c00000 -#define BCM_DEVICE1_BASE GICD_BASE + +#define SMBUS0_BASE 0x689b0000 +#define SMBUS0_END (SMBUS0_BASE + 0xB0) + +#define SECURE_GPIO_BASE0 0x689d0000 +#define ASIU_GPIO_INTR 190 +#define GPIO_NUM_START0 0 +#define NUM_GPIOS0 256 +#define SPI_0_BASE 0x68a80000 +#define SPI_0_END (SPI_0_BASE + 0x1000) +#define SPI_0_CLK_HZ 175000000 +#define SPI_0_CS_MUX_PAD 0x68a40490 + +#define HWRNG_BASE 0x68b20000 +#define HWRNG_END (HWRNG_BASE + 0x28) + +#define SOTP_BASE 0x68b50000 + +/* device memory ranges */ +#define BCM_DEVICE0_BASE GICD_BASE +#define BCM_DEVICE0_SIZE CORE_MMU_PGDIR_SIZE +#define BCM_DEVICE1_BASE SMBUS0_BASE #define BCM_DEVICE1_SIZE CORE_MMU_PGDIR_SIZE -#else -#error "Unknown platform flavor" -#endif +/* NS DDR ranges */ +#define BCM_DRAM0_NS_BASE 0x80000000 +#define BCM_DRAM0_NS_SIZE 0x0d000000 +#define BCM_DRAM1_NS_BASE 0x90000000 +#define BCM_DRAM1_NS_SIZE 0x70000000 +#define BCM_DRAM2_NS_BASE 0x880400000 +#define BCM_DRAM2_NS_SIZE 0x17fbfffff + #endif /*PLATFORM_CONFIG_H*/ |