core: arm: imx: handle errata 845369

Under very rare timing circumstances, a data corruption might occur on
a dirty cache line that is evicted from the L1 Data Cache due to another
cache line being entirely written.
Configurations affected:
This erratum affects configurations with either:
- One processor if the ACP is present
- Two or more processors

This erratum can be worked round by setting bit[22] of the undocumented
Diagnostic Control Register to 1. This register is encoded as
CP15 c15 0 c0 1. The bit can be written in Secure state only, with the
following.
Read/Modify/Write code sequence:
MRC p15,0,rt,c15,c0,1
ORR rt,rt,#0x00400000
MCR p15,0,rt,c15,c0,1

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>

1 files changed, 30 insertions, 0 deletions

diff --git a/core/arch/arm/plat-imx/a9_plat_init.S b/core/arch/arm/plat-imx/a9_plat_init.S
index 8a11198f..0df68afb 100644
--- a/core/arch/arm/plat-imx/a9_plat_init.S
+++ b/core/arch/arm/plat-imx/a9_plat_init.S
@@ -3,6 +3,7 @@
  * Copyright (c) 2014, STMicroelectronics International N.V.
  * Copyright (c) 2016, Wind River Systems.
  * All rights reserved.
+ * Copyright 2019 NXP
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -58,6 +59,35 @@ FUNC plat_cpu_reset_early , :
 UNWIND(	.fnstart)
 
 	/*
+	 * Under very rare timing circumstances, transition into streaming
+	 * mode might create a data corruption
+	 * Configurations affected
+	 * This erratum affects configurations with either:
+	 * - One processor if the ACP is present
+	 * - Two or more processors
+	 * This erratum can be worked round by setting bit[22] of the
+	 * undocumented Diagnostic Control Register to 1. This
+	 * register is encoded as CP15 c15 0 c0 1.
+	 * The bit can be written in Secure state only, with the following
+	 * Read/Modify/Write code sequence:
+	 * MRC p15,0,rt,c15,c0,1
+	 * ORR rt,rt,#0x00400000
+	 * MCR p15,0,rt,c15,c0,1
+	 * When this bit is set, the processor is unable to switch into
+	 * Read-Allocate (streaming) mode, which means this erratum cannot
+	 * occur. Setting this bit could possibly result in a visible drop
+	 * in performance for routines that perform intensive memory
+	 * accesses, such as memset() or memcpy(). However, the workaround
+	 * is not expected to create any significant performance degradation
+	 * in most standard applications.
+	 */
+#if defined(CFG_MX6QP) || defined(CFG_MX6Q) || defined(CFG_MX6D) || \
+	 defined(CFG_MX6DL)
+	read_diag r0
+	orr r0, r0, #1 << 22
+	write_diag r0
+#endif
+	/*
 	 * Disallow NSec to mask FIQ [bit4: FW=0]
 	 * Allow NSec to manage Imprecise Abort [bit5: AW=1]
 	 * Imprecise Abort trapped to Abort Mode [bit3: EA=0]