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The ccu-sun50i-a64 table (upstream, in Linux) has the multiplier and
divider for creating the 'osc12M' instance from 'osc24M' backwards,
thus creating a 48M clock.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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The SPI controller in the Allwinner A64 SoC supports dual-IO for
the RX phase of transmission. This can be used with the command
'fast read dual output' (cmd, addr and dummy byte are transmitted
in single-IO mode; data is received in dual-IO mode) to quickly
read out SPI flashes, when the device-tree marks the flash as
having 'spi-rx-bus-width = <2>'.
Unfortunately, the SPI-NOR flash layer in U-Boot does not manage
the single-IO and dual-IO transition (partially due to the fact
that spi_xfer(...) does not allow to convery such information),
but correctly chooses the FAST_READ_DUAL_OUTPUT (0x3b) opcode.
The net result of this is that a dual-IO read is initiated, but
the data reception will capture only every other bit...
This change puts a temporary fix in place, which identifies a
0x3b opcode being sent in a transaction with a SPI flash and then
manages the switching to dual-IO within the driver.
This change should be reverted, once more permanent solutions
in the higher layers and in the SPI driver model have been agreed
on and have been put in place.
Tested on an A64 (sun50iw1p1) against a Winbond W25Q80DV flash at
up to 100MHz (i.e. 200MBit/s read bursts).
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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This adds a rewrite of the SPI driver we had in use for the A31-uQ7
(sun6i), A80-Q7 (sun9i) and A64-uQ7 (sun50i) boards, which includes
support for:
* cs-gpios (i.e. GPIOs as additional chip-selects)
* clocking, reset and pinctrl based on the device-model
* dual-IO data receive for controllers that support it (sun50i)
The key difference to the earlier incarnation that we provided as part
of our BSP is the removal of the legacy reset and clocking code and
added resilience to configuration errors (i.e. timeouts for the inner
loops) and converstion to the device-model. This was possible due to a
non-device-model driver now being present for use with in the SPL.
This has been verified against the A64-uQ7 with data rates up to
100MHz and dual-IO ("Fast Read Dual Output" opcode) from the on-board
SPI-NOR flash.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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The I2C block in sunxi (Allwinner SoCs) is based on Designware and uses
the same driver as the Marvell Orion 5x and Kirkwood families.
This change adds a compatible id matching the binding for sunxi
devices, supports configuring the clocks and to release the module
reset on sunxi platforms as directed by the device tree.
As we enable DT control of this driver, we need to make sure the
common config header (sunxi-common.h) does try to turn on support for
the legacy I2C support.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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We now support the device-model for configuration of the driver
including the interface to the pinctrl, reset and clock frameworks.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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parse_phy_pins() is parsing the pinctrl-entry of the emac-node, which
is in conflict with the new DM pinctrl driver for sun50i. So when
building for sun50i and if the pinctrl driver is active, let the
parse_phy_pins()-function do nothing.
Use the DM reset and DM clk frameworks for getting the emac module out
of reset and enabling the clock gates.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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When CONFIG_CLK is defined, we now provide support for the basic
clock configuration of peripherals on sunxi:
* clk-sunxi-ccu.c implements the CCU based (new-style) binding
based on the Linux implementation.
And for handling the binding of the always-on (R_*) subsystems:
* clk-sunxi-mod.c implements support for module clocks, which
performs parent selection (determined via the device-tree)
and determines/configures a pre-divider and divider when
setting a clock-rate
* clk-sunxi-gate.c: implements an clk-gate to gate individual
modules (i.e. 'allwinner,sunxi-multi-bus-gates-clk')
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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In order to have the device model describe the module reset bits
on sunxi (well, at least for anything newer than sun6i), we need
a (rather simple) driver for 'allwinner,sun6i-a31-clock-reset'
nodes.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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Our gpio and pinctrl driver need to be bound against the same
node. While this can be done by hand (i.e. explicitly looking up the
driver, creating the driver-data and binding the device), it is much
easier done when the new option for the binding of multiple drivers
against a single node is configured.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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Currently, driver binding stops once it encounters the first
compatible driver that doesn't refuse to bind. However, there are
cases where a single node will need to be handled by multiple driver
classes. For those cases we provide a configurable option to continue
to bind after the first driver has been found.
The first use cases for this are from the DM conversion of the sunxi
(Allwinner) architecture:
* pinctrl (UCLASS_PINCTRL) and gpio (UCLASS_GPIO) drivers need to
bind against a single node
* clock (UCLASS_CLK) and reset (UCLASS_RESET) drivers also need to
bind against a single node
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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This change adds a full device-model pinctrl driver for sunxi (tested with
sun50iw1p1) based on the support available in Linux.
Details are:
* implements a driver for pinctrl devices and assigns sun50i-a64-pinctrl
and sun50i-a64-r-pinctrl to it
* dynamically creates the driver_data for a sunxi_gpio (see sunxi_gpio.c)
driver and binds it to the same device-tree node
* lifts and reuses the pinctrl-sunxi.h and pinctrl-sun50i-a64.c files from
Linux (thanks to Maxime and Andre) and adds a pinctrl-sun50i-a64-r.c (to
be picked up for inclusion into Linux again)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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Note that this assumes that R_PIO is already clocked (usually by ATF,
which will need to enable the clock-gate to R_PIO when starting AXP
communication through R_RSB).
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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This changeset moves two configuration options into Kconfig:
* PHY_GIGE, indicates that a controller (with an appropriate PHY) is
Gigabit capable and enables extra support in the miiutil for
parsing the status of Gigabit PHYs
* individual configuration options for MICREL_KSZ9021 and
MICREL_KSZ9031 GbE PHYs, which previously had to enabled through
a board-specific config file
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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This ports the support for configuring a GPIO for resetting the
Ethernet PHY (incl. such details as the reset polarity and
pulse-length) from the Designware driver.
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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The MDIO read/write builds up the MII_CMD register from scratch (starting
with a value of 0). No need to mask out any fields before writing the new
values.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The IEEE 802.3 standard guarantees operation of the MDIO signals at up
to 2.5MHz (anything above this is a vendor-specific feature, although
most PHYs work at higher frequencies). With the EMAC being fed by a
(typically) 300MHz clock (e.g. on the A64 this is AHB2, which should
be kept at 300MHz according to the CCU documentation), we need to use
the divide-by-128 setting to get us below 2.5MHz.
The ~2.34MHz clock signal (i.e. assuring that the MDC clock is indeed
derived from the AHB2 clock) has been verified using a A64-uQ7.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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A number of designs will have GPIOs connected to external USB devices
to keep them in reset while the associated USB controller is inactive.
E.g. on the A64-uQ7 we have individual enable GPIOs for each USB hub
cascaded on EHCI1 and customers can use any available GPIO to control
USB devices on the baseboard.
By moving this into the DTS we can easily specify a list of GPIOs and
even model their polarity (active-low vs. active-high).
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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These changes add support for MUSB (OTG) and HCI1 on sun50i (A64)
and try to improve documentation:
* adds support for the shared PHY (MUSB and OTG-EHCI/OTG-OHCI) on
sun50i (A64) in musb-new/sunxi.c to automatically change the
PHY routing when opening/closing MUSB
* sets up the usb_phy_passby only from the HCI ([eo]hci_sunxi.c)
init and does not match on the PHY id (id #0 is either used by
MUSB or by OTG-EHCI/OHCI) in the common PHY initialisation
* adds support for clearing the 'SIDDP' bit in the PHYCTL register
(and left a comment for the H3, which apparently does the same
from sunxi_usb_phy_config in a 'magic' write)
* introduced a SUNXI_MUSB_BASE define for the MUSB driver to find
the controller (it's usually USB0_BASE, but not on the A64 where
USB0_BASE is the OTG-EHCI/OHCI address space) ... this should
eventually disappear entirely, as the sunxi musb support moves
to support the device model
* added initialisation calls to clearing the 'SIDDP' bit in the
PHYCTL register and for the usb_phy_passby to ehci-sunxi.c and
ohci-sunxi.c (note that these are idempotent, so we don't need
to worry that we call this multiple times)
* updated the comments in 'sunxi_usb_phy_config' based on the
English comments in Allwinner's 3.10 kernel release
* add additional defines for the clock gating and module reset bits
for the somewhat different controller configuration in the A64,
partially motivated by the fact that the musb-new/sunxi.c glue
expects AHB_GATE_OFFSET_USB0 to be the bit number for MUSB.
Note (for testers) that turning on the complete USB hub cascade
connected to EHCI1 on the A64-uQ7 requires two GPIOs, so you will need
to either have the (separate) change for having multiple GPIOs in your
tree or issue the command 'gpio set pe4' to turn on the second
(cascaded) hub.
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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The sun50i platform (e.g. the A64/sun50iw1p1) integrates 2 USB PHYs
which are connected as follows:
PHY#0 is shared between the OTG controller (MUSB) [at 01C19000]
and the USB-OTG-HCI [at 01C1A000]
PHY#1 is dedicated to USB-HCI0 [at 01C1B000] and can be bypassed
when connecting HCI0 to the HSIC interface
Note that all USB PHYs are controlled from within the OTG address
space at 01C19000.
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Throughput tests have shown the sunxi_mmc driver to take over 10s to
read 10MB from a fast eMMC device due to excessive delays in polling
loops.
This commit restructures the main polling loops to use get_timer(...)
to determine whether a (millisecond) timeout has expired. We choose
not to use the wait_bit function, as we don't need interruptability
with ctrl-c and have at least one case where two bits (one for an
error condition and another one for completion) need to be read and
using wait_bit would have not added to the clarity.
The observed speedup in testing is greater than 10x (e.g. a 10MB write
decreases from 9.302s to 0.884s).
X-Affected-platforms: A31-uQ7, A80-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
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The sunxi-specific SPI load routine only knows how to load a legacy
U-Boot image.
Teach it how to handle FIT images as well, simply by providing the
existing SPL FIT loader with the right loader routine to access the SPI
NOR flash.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The driver model display driver is based on sunxi_display.c
It is currently backwards compatible with the console driver (which
is not driver-model, see TODOs)
Devices can be defined via the dts
Note that using of reg base addresses from dts is only partly implemented,
since some functions in the old sunxi_display are used by both hdmi and
lvds modes; these would need to be separated (or both addresses have to
be specified in the device tree) (see TODOs)
Currently supported modes:
* lvds: single-channel
* hdmi (with EDID)
Currently unsupported modes:
* parallel lcd
* vga
Signed-off-by: Octav Zlatior <octav.zlatior@theobroma-systems.com>
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switch to ACIN even if it's shorted with VBUS
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
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"unsigned long" is a lousy data type when it comes to match peripheral
hardware registers with a fixed size.
Just do the obvious and match a 32-bit display format with an "u32"
data type for casting.
This fixes the logo display on 64-bit architectures, which produced
a black line on the right side of the logo with non-black backgrounds.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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When the zynq_gem driver initializes the phy it sets the supported
features that the phy can support and advertise. However instead of
masking the supported features such that it limits the available
features it sets the phy to have the exact supported features of the
zynq_gem. This is problematic as it will enable features that a phy does
not have or cannot advertise.
Specifically this appears as an issue when using a phy that is only
capable of 10/100, but the zynq_gem driver will override this and try to
enable and advertise 10/100/1000.
Reported-by: Arno Steffens <star@gmx.li>
Fixes: 80243528ef ("net: gem: Fix gem driver on 1Gbps LAN")
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Tested-by: Arno Steffens <star@gmx.li>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
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For the boards such as smartweb on which the clock driver isn't
supported, the ethernet fail to be found when booting up with
the below log.
---8<---
Net: No ethernet found.
--->8---
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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There is one "0" too many in 83500000 mpixelclock in rockchip_mpll_cfg[].
fix it.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
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With this patch, USB Command Verifier is happy with our DFU
implementation on Chapter 9 tests.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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instead of only copying if strlen(s) is less than 32 characters, let's
just copy at most 31 characters regardless of the size of
serial#. This will guarantee that we always have a serial number if
serial# environment variable is set to anything.
Note that without a proper serial number, USB Command Verifier fails
our test of Device Descriptor since we will claim to have a serial
number without really providing one when requested.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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If last packet is short, we shouldn't write req->length bytes to
non-volatile media, we should write only what's available to us, which
is held in req->actual.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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harmonize result with other handle_XXX() functions: return int for size
remove the define RET_STAT_LEN : no more necessary
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
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return the correct size for DFU_GETSTATE result (1 byte in DFU 1.1 spec)
to avoid issue in USB protocol and the variable "value" is propagated
to req->lenght as all the in the other request with answer
- DFU_GETSTATUS
- DFU_DNLOAD
- DFU_UPLOAD
Then the buffer is correctly treated in USB driver
NB: it was the only request witch directly change "req->actual"
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
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The "DFU descriptor set" must contain the "DFU functional descriptor"
but it is missing today in U-Boot code
(cf: DFU spec 1.1, chapter 4.2 DFU Mode Descriptor Set)
This patch only allocate buffer and copy DFU functional descriptor
after interfaces.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
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Remove sys_proto.h inclusion which is not used by the driver.
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Support the following DT properties:
"bias-disable"
"bias-pull-up"
"bias-pull-down"
"bias-pull-pin-default"
"input-enable"
"input-disable"
My main motivation is to support pull up/down biasing. For Pro5 and
later SoCs, the pupdctrl register number is the same as the pinmux
number, so this feature can be supported without having big pin
tables.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Currently the system hangs when the 'videomode' variable is not present
and a reset command is issued:
=> setenv videomode
=> saveenv
=> reset
(Board hangs)
lcdif_power_down() assumes that the LCDIF controller has been properly
configured and enabled, which may not be true.
To fix this issue check whether panel.frameAdrs has been initialized and
in case it has not been initialized, do not continue with the LCDIF
powerdown sequence.
Tested on a imx7dsabresd board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
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