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-rw-r--r--drivers/reset/Kconfig9
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/sunxi/Makefile6
-rw-r--r--drivers/reset/sunxi/ccu-sun50i-a64.c75
-rw-r--r--drivers/reset/sunxi/ccu_reset.h9
-rw-r--r--drivers/reset/sunxi/reset-sunxi.c168
6 files changed, 268 insertions, 0 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bcf0e..8db25fc834 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -43,4 +43,13 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
+config RESET_SUNXI
+ bool "Reset controller driver for Allwiner SoCs"
+ depends on DM_RESET && ARCH_SUNXI
+ default y
+ help
+ Support for reset controllers on Allwinner SoCs.
+ Say Y if you want to control reset signals provided by CCU (e.g. sun50i)
+ or PRCM (e.g. sun6i, sun9i) blocks.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305cc1d..a4994e9645 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_RESET_SUNXI) += sunxi/
diff --git a/drivers/reset/sunxi/Makefile b/drivers/reset/sunxi/Makefile
new file mode 100644
index 0000000000..559c79a2fd
--- /dev/null
+++ b/drivers/reset/sunxi/Makefile
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset-sunxi.o
+obj-$(CONFIG_MACH_SUN50I) += ccu-sun50i-a64.o \ No newline at end of file
diff --git a/drivers/reset/sunxi/ccu-sun50i-a64.c b/drivers/reset/sunxi/ccu-sun50i-a64.c
new file mode 100644
index 0000000000..f7c388e875
--- /dev/null
+++ b/drivers/reset/sunxi/ccu-sun50i-a64.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * The tabular data contained in this file is reused verbatim from
+ * Linux (drivers/clk/sunxi-ng.c), which is:
+ * Copyright (c) 2016 Maxime Ripard. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
+
+#include "ccu_reset.h"
+
+const struct ccu_reset_map sun50i_a64_ccu_resets[] = {
+ [RST_USB_PHY0] = { 0x0cc, BIT(0) },
+ [RST_USB_PHY1] = { 0x0cc, BIT(1) },
+ [RST_USB_HSIC] = { 0x0cc, BIT(2) },
+
+ [RST_DRAM] = { 0x0f4, BIT(31) },
+ [RST_MBUS] = { 0x0fc, BIT(31) },
+
+ [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
+ [RST_BUS_CE] = { 0x2c0, BIT(5) },
+ [RST_BUS_DMA] = { 0x2c0, BIT(6) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
+ [RST_BUS_NAND] = { 0x2c0, BIT(13) },
+ [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
+ [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
+ [RST_BUS_TS] = { 0x2c0, BIT(18) },
+ [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
+ [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
+ [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
+ [RST_BUS_OTG] = { 0x2c0, BIT(23) },
+ [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
+ [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
+ [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
+ [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
+
+ [RST_BUS_VE] = { 0x2c4, BIT(0) },
+ [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
+ [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
+ [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
+ [RST_BUS_CSI] = { 0x2c4, BIT(8) },
+ [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
+ [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
+ [RST_BUS_DE] = { 0x2c4, BIT(12) },
+ [RST_BUS_GPU] = { 0x2c4, BIT(20) },
+ [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
+ [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
+ [RST_BUS_DBG] = { 0x2c4, BIT(31) },
+
+ [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
+
+ [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
+ [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
+ [RST_BUS_THS] = { 0x2d0, BIT(8) },
+ [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
+ [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
+ [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
+
+ [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
+ [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
+ [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
+ [RST_BUS_SCR] = { 0x2d8, BIT(5) },
+ [RST_BUS_UART0] = { 0x2d8, BIT(16) },
+ [RST_BUS_UART1] = { 0x2d8, BIT(17) },
+ [RST_BUS_UART2] = { 0x2d8, BIT(18) },
+ [RST_BUS_UART3] = { 0x2d8, BIT(19) },
+ [RST_BUS_UART4] = { 0x2d8, BIT(20) },
+};
diff --git a/drivers/reset/sunxi/ccu_reset.h b/drivers/reset/sunxi/ccu_reset.h
new file mode 100644
index 0000000000..83b30a01e8
--- /dev/null
+++ b/drivers/reset/sunxi/ccu_reset.h
@@ -0,0 +1,9 @@
+#ifndef _CCU_RESET_H_
+#define _CCU_RESET_H_
+
+struct ccu_reset_map {
+ uint16_t reg;
+ uint32_t bit;
+};
+
+#endif /* _CCU_RESET_H_ */
diff --git a/drivers/reset/sunxi/reset-sunxi.c b/drivers/reset/sunxi/reset-sunxi.c
new file mode 100644
index 0000000000..8fbfa85b91
--- /dev/null
+++ b/drivers/reset/sunxi/reset-sunxi.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <reset-uclass.h>
+#include <dm/device.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#include "ccu_reset.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sunxi_reset_priv {
+ void *base;
+ size_t size;
+};
+
+static int sunxi_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s (%s): id %ld\n",
+ reset_ctl->dev->name, __func__, reset_ctl->id);
+ return 0;
+}
+
+static int sunxi_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s (%s): id %ld\n",
+ reset_ctl->dev->name, __func__, reset_ctl->id);
+ return 0;
+}
+
+static int sunxi_reset_update_bit(struct udevice *dev,
+ const uint32_t off,
+ const uint32_t bitmask,
+ const bool assert)
+{
+ const struct sunxi_reset_priv *priv = dev_get_priv(dev);
+
+ debug("%s (%s): base %p offset %x bit %x assert %d size %ld\n",
+ dev->name, __func__,
+ priv->base, off, bitmask, assert, priv->size);
+
+ if (off >= priv->size)
+ return -EINVAL;
+
+ if (assert)
+ clrbits_le32(priv->base + off, bitmask);
+ else
+ setbits_le32(priv->base + off, bitmask);
+
+ return 0;
+}
+
+static int sunxi_ccu_reset_update(struct reset_ctl *reset_ctl, bool assert)
+{
+ struct udevice *dev = reset_ctl->dev;
+ const struct ccu_reset_map *reset_map =
+ (const struct ccu_reset_map *)dev_get_driver_data(dev);
+ const struct ccu_reset_map *entry = &reset_map[reset_ctl->id];
+
+ return sunxi_reset_update_bit(dev, entry->reg, entry->bit, assert);
+}
+
+static int sunxi_ccu_reset_assert(struct reset_ctl *reset_ctl)
+{
+ return sunxi_ccu_reset_update(reset_ctl, true);
+}
+
+static int sunxi_ccu_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ return sunxi_ccu_reset_update(reset_ctl, false);
+}
+
+static int sunxi_reset_update(struct reset_ctl *reset_ctl, bool assert)
+{
+ struct udevice *dev = reset_ctl->dev;
+ const unsigned long id = reset_ctl->id;
+ const unsigned long offset = (id / 32) * sizeof(uint32_t);
+ const unsigned int bit = id % 32;
+
+ return sunxi_reset_update_bit(dev, offset, BIT(bit), assert);
+}
+
+static int sunxi_reset_assert(struct reset_ctl *reset_ctl)
+{
+ return sunxi_reset_update(reset_ctl, true);
+}
+
+static int sunxi_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ return sunxi_reset_update(reset_ctl, false);
+}
+
+static int sunxi_reset_probe(struct udevice *dev)
+{
+ struct sunxi_reset_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+ "reg", 0, &size, false);
+ if (addr == FDT_ADDR_T_NONE) {
+ debug("%s: failed to find base address ('reg')\n", dev->name);
+ return -ENODEV;
+ }
+ priv->base = (void *)addr;
+ priv->size = size;
+
+ if (!priv->base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static const struct reset_ops sunxi_reset_ops = {
+ .request = sunxi_reset_request,
+ .free = sunxi_reset_free,
+ .rst_assert = sunxi_reset_assert,
+ .rst_deassert = sunxi_reset_deassert,
+};
+
+static const struct udevice_id sunxi_reset_match[] = {
+ { .compatible = "allwinner,sun6i-a31-clock-reset" },
+ { }
+};
+
+
+U_BOOT_DRIVER(sunxi_reset) = {
+ .name = "sunxi-reset",
+ .id = UCLASS_RESET,
+ .of_match = sunxi_reset_match,
+ .ops = &sunxi_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct sunxi_reset_priv),
+ .probe = sunxi_reset_probe,
+};
+
+static const struct reset_ops sunxi_ccu_reset_ops = {
+ .request = sunxi_reset_request,
+ .free = sunxi_reset_free,
+ .rst_assert = sunxi_ccu_reset_assert,
+ .rst_deassert = sunxi_ccu_reset_deassert,
+};
+
+#if defined(CONFIG_MACH_SUN50I)
+extern const struct ccu_reset_map sun50i_a64_ccu_resets;
+#endif
+
+static const struct udevice_id sunxi_ccu_reset_match[] = {
+#if defined(CONFIG_MACH_SUN50I)
+ { .compatible = "allwinner,sun50i-a64-ccu",
+ .data = (ulong)&sun50i_a64_ccu_resets },
+#endif
+ { }
+};
+
+U_BOOT_DRIVER(sunxi_ccu_reset) = {
+ .name = "sunxi-ccu-reset",
+ .id = UCLASS_RESET,
+ .of_match = sunxi_ccu_reset_match,
+ .ops = &sunxi_ccu_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct sunxi_reset_priv),
+ .probe = sunxi_reset_probe,
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 15:01:50 +0000