diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2016-05-17 18:40:25 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-03-09 01:40:05 +0100 |
| commit | b778380c0b9d080cc76a7630cfd938b164fe05da (patch) | |
| tree | 031970477a62b4499afa8e1cdf88ab066aec7842 /arch | |
| parent | c0f4e26f714ac0f7b8d1928488c14f25b7d52e1d (diff) | |
[fix] clock_sun6i merge fixes
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-sunxi/clock_sun6i.c | 37 |
1 files changed, 13 insertions, 24 deletions
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 81c87f8aee..3cbfaead79 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -35,8 +35,8 @@ void clock_init_safe(void) clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, PRCM_PLL_CTRL_LDO_KEY); clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, - PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | - PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) ); + PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) ); clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); #endif @@ -48,12 +48,21 @@ void clock_init_safe(void) */ sdelay(100000); + /* Reinitialise PLL1 (CPUX) to 408MHz */ clock_set_pll1(408000000); + /* Enable PLL6 at 600MHz */ + clock_pll6_init(); writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); - /* Enable PLL6 at 600MHz */ - clock_pll6_init(); + { + /* Release GPIO clock gate and de-assert the GPIO reset */ + setbits_le32(0x01c20068, (1 << 5)); + /* Configure PH7 as an output */ + clrsetbits_le32(0x01C208fc, (0b111 << 28), (0b001 << 28)); + /* Output LOW on PH7 */ + clrbits_le32(0x01C2010c, (1 << 7)); + } writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); if (IS_ENABLED(CONFIG_MACH_SUN6I)) @@ -101,25 +110,6 @@ void clock_init_uart(void) #endif } -int clock_twi_onoff(int port, int state) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - if (port > 3) - return -1; - - /* set the apb clock gate for twi */ - if (state) - setbits_le32(&ccm->apb2_gate, - CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port)); - else - clrbits_le32(&ccm->apb2_gate, - CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port)); - - return 0; -} - static inline void wait_for_pll_lock(u32 *reg) { do { @@ -228,7 +218,6 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) wait_for_pll_lock(&ccm->pll5_cfg); } -<<<<<<< HEAD:arch/arm/mach-sunxi/clock_sun6i.c #ifdef CONFIG_MACH_SUN6I void clock_set_mipi_pll(unsigned int clk) { |