Merge branch 'master' of http://git.denx.de/u-boot-sunxi

15 files changed, 153 insertions, 28 deletions

diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c
index 19bb5a1fe5..6ac96ccf86 100644
--- a/arch/arm/cpu/armv7/sunxi/usb_phy.c
+++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c
@@ -31,6 +31,9 @@
 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN	(1 << 8)
 #define SUNXI_EHCI_ULPI_BYPASS_EN	(1 << 0)
 
+#define REG_PHY_UNK_H3			0x420
+#define REG_PMU_UNK_H3			0x810
+
 static struct sunxi_usb_phy {
 	int usb_rst_mask;
 	int gpio_vbus;
@@ -39,19 +42,30 @@ static struct sunxi_usb_phy {
 	int id;
 	int init_count;
 	int power_on_count;
+	int base;
 } sunxi_usb_phy[] = {
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
 		.id = 0,
+		.base = SUNXI_USB0_BASE,
 	},
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
 		.id = 1,
+		.base = SUNXI_USB1_BASE,
 	},
 #if CONFIG_SUNXI_USB_PHYS >= 3
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
 		.id = 2,
+		.base = SUNXI_USB2_BASE,
+	},
+#endif
+#if CONFIG_SUNXI_USB_PHYS >= 4
+	{
+		.usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
+		.id = 3,
+		.base = SUNXI_USB3_BASE,
 	}
 #endif
 };
@@ -114,6 +128,15 @@ static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
 	}
 }
 
+#if defined CONFIG_MACH_SUN8I_H3
+static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
+{
+	if (phy->id == 0)
+		clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
+
+	clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
+}
+#else
 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 {
 	/* The following comments are machine
@@ -136,16 +159,14 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 
 	return;
 }
+#endif
 
-static void sunxi_usb_phy_passby(int index, int enable)
+static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
 {
 	unsigned long bits = 0;
 	void *addr;
 
-	if (index == 1)
-		addr = (void *)SUNXI_USB1_BASE + SUNXI_USB_PMU_IRQ_ENABLE;
-	else
-		addr = (void *)SUNXI_USB2_BASE + SUNXI_USB_PMU_IRQ_ENABLE;
+	addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
 
 	bits = SUNXI_EHCI_AHB_ICHR8_EN |
 		SUNXI_EHCI_AHB_INCR4_BURST_EN |
@@ -181,7 +202,7 @@ void sunxi_usb_phy_init(int index)
 	sunxi_usb_phy_config(phy);
 
 	if (phy->id != 0)
-		sunxi_usb_phy_passby(index, SUNXI_USB_PASSBY_EN);
+		sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
 }
 
 void sunxi_usb_phy_exit(int index)
@@ -194,7 +215,7 @@ void sunxi_usb_phy_exit(int index)
 		return;
 
 	if (phy->id != 0)
-		sunxi_usb_phy_passby(index, !SUNXI_USB_PASSBY_EN);
+		sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
 
 	clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
 }
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 554d8589ed..9de7754bb0 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -229,8 +229,18 @@ struct sunxi_ccm_reg {
 /* ahb_gate0 offsets */
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29
+#ifdef CONFIG_MACH_SUN8I_H3
+/*
+ * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define AHB_GATE_OFFSET_USB_EHCI2	27
+#define AHB_GATE_OFFSET_USB_EHCI1	26
+#define AHB_GATE_OFFSET_USB_EHCI0	25
+#else
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
+#endif
 #define AHB_GATE_OFFSET_USB0		24
 #define AHB_GATE_OFFSET_MCTL		14
 #define AHB_GATE_OFFSET_GMAC		17
@@ -263,13 +273,25 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_PHY3_RST (0x1 << 3)
 /* There is no global phy clk gate on sun6i, define as 0 */
 #define CCM_USB_CTRL_PHYGATE 0
 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
+#ifdef CONFIG_MACH_SUN8I_H3
+/*
+ * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#else
 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#endif
 
 #define CCM_GMAC_CTRL_TX_CLK_SRC_MII	0x0
 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 0cdefdcdf4..b6e11eb8ea 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -52,10 +52,18 @@
 #define SUNXI_USB2_BASE			0x01c1c000
 #endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
+#ifdef CONFIG_MACH_SUN8I_H3
+#define SUNXI_USBPHY_BASE		0x01c19000
+#define SUNXI_USB0_BASE			0x01c1a000
+#define SUNXI_USB1_BASE			0x01c1b000
+#define SUNXI_USB2_BASE			0x01c1c000
+#define SUNXI_USB3_BASE			0x01c1d000
+#else
 #define SUNXI_USB0_BASE			0x01c19000
 #define SUNXI_USB1_BASE			0x01c1a000
 #define SUNXI_USB2_BASE			0x01c1b000
 #endif
+#endif
 #define SUNXI_CSI1_BASE			0x01c1d000
 #define SUNXI_TZASC_BASE		0x01c1e000
 #define SUNXI_SPI3_BASE			0x01c1f000
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index a334aa336d..5e9d3af336 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -372,11 +372,14 @@ config I2C3_ENABLE
 	See I2C0_ENABLE help text.
 endif
 
+if SUNXI_GEN_SUN6I
 config R_I2C_ENABLE
 	bool "Enable the PRCM I2C/TWI controller"
-	default n
+	# This is used for the pmic on H3
+	default y if SY8106A_POWER
 	---help---
 	Set this to y to enable the I2C controller which is part of the PRCM.
+endif
 
 if MACH_SUN7I
 config I2C4_ENABLE
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 420481a9fb..15b7af634c 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -25,6 +25,7 @@
 #include <asm/io.h>
 #include <nand.h>
 #include <net.h>
+#include <sy8106a.h>
 
 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
@@ -436,6 +437,10 @@ void sunxi_board_init(void)
 	int power_failed = 0;
 	unsigned long ramsize;
 
+#ifdef CONFIG_SY8106A_POWER
+	power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
+#endif
+
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
 	defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
 	power_failed = axp_init();
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index ea9ed874e8..aaf0f68c35 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -12,4 +12,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
-CONFIG_R_I2C_ENABLE=y
+CONFIG_SY8106A_POWER=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 003a9c6c03..e52dcfc718 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -12,3 +12,5 @@ CONFIG_SPL=y
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_SY8106A_POWER=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 10683a21d9..adc64552e7 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -48,6 +48,13 @@ config AXP818_POWER
 	Say y here to enable support for the axp818 pmic found on
 	A83T dev board.
 
+config SY8106A_POWER
+	boolean "SY8106A pmic support"
+	depends on MACH_SUN8I_H3
+	---help---
+	Select this to enable support for the SY8106A pmic found on some
+	H3 boards.
+
 endchoice
 
 config AXP_DCDC1_VOLT
@@ -232,4 +239,13 @@ config AXP_ELDO3_VOLT
 	1.2V for the SSD2828 chip (converter of parallel LCD interface
 	into MIPI DSI).
 
+config SY8106A_VOUT1_VOLT
+	int "SY8106A pmic VOUT1 voltage"
+	depends on SY8106A_POWER
+	default 1200
+	---help---
+	Set the voltage (mV) to program the SY8106A pmic VOUT1. This
+	is typically used to power the VDD-CPU and should be 1200mV.
+	Values can range from 680mV till 1950mV.
+
 endmenu
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 0fdbca3c35..690faa0f5e 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_AXP221_POWER)	+= axp221.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
+obj-$(CONFIG_SY8106A_POWER)	+= sy8106a.o
 obj-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o
 obj-$(CONFIG_TWL4030_POWER)	+= twl4030.o
 obj-$(CONFIG_TWL6030_POWER)	+= twl6030.o
diff --git a/drivers/power/sy8106a.c b/drivers/power/sy8106a.c
new file mode 100644
index 0000000000..bbf116f655
--- /dev/null
+++ b/drivers/power/sy8106a.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2016
+ * Jelle van der Waa <jelle@vdwaa.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+#include <sy8106a.h>
+
+#define SY8106A_I2C_ADDR 0x65
+#define SY8106A_VOUT1_SEL 1
+#define SY8106A_VOUT1_SEL_ENABLE (1 << 7)
+
+static u8 sy8106a_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+	if (mvolt < min)
+		mvolt = min;
+	else if (mvolt > max)
+		mvolt = max;
+
+	return (mvolt - min) / div;
+}
+
+int sy8106a_set_vout1(unsigned int mvolt)
+{
+	u8 data = sy8106a_mvolt_to_cfg(mvolt, 680, 1950, 10) | SY8106A_VOUT1_SEL_ENABLE;
+	return i2c_write(SY8106A_I2C_ADDR, SY8106A_VOUT1_SEL, 1, &data, 1);
+}
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index d494ca10bb..cf3dcc4327 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -35,13 +35,12 @@ static int ehci_usb_probe(struct udevice *dev)
 	 * This should go away once we've moved to the driver model for
 	 * clocks resp. phys.
 	 */
-	if (hccr == (void *)SUNXI_USB1_BASE) {
-		priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
-		priv->phy_index = 1;
-	} else {
-		priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1;
-		priv->phy_index = 2;
-	}
+	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
+#ifdef CONFIG_MACH_SUN8I_H3
+	priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
+#endif
+	priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
+	priv->ahb_gate_mask <<= priv->phy_index - 1;
 
 	setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -83,6 +82,7 @@ static const struct udevice_id ehci_usb_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-ehci", },
 	{ .compatible = "allwinner,sun7i-a20-ehci", },
 	{ .compatible = "allwinner,sun8i-a23-ehci", },
+	{ .compatible = "allwinner,sun8i-h3-ehci",  },
 	{ .compatible = "allwinner,sun9i-a80-ehci", },
 	{ }
 };
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index 60792726ee..1b1f651697 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -37,15 +37,14 @@ static int ohci_usb_probe(struct udevice *dev)
 	 * This should go away once we've moved to the driver model for
 	 * clocks resp. phys.
 	 */
-	if (regs == (void *)(SUNXI_USB1_BASE + 0x400)) {
-		priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
-		priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
-		priv->phy_index = 1;
-	} else {
-		priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI1;
-		priv->usb_gate_mask = CCM_USB_CTRL_OHCI1_CLK;
-		priv->phy_index = 2;
-	}
+	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
+#ifdef CONFIG_MACH_SUN8I_H3
+	priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
+#endif
+	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+	priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
+	priv->ahb_gate_mask <<= priv->phy_index - 1;
+	priv->usb_gate_mask <<= priv->phy_index - 1;
 
 	setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
 	setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
@@ -86,6 +85,7 @@ static const struct udevice_id ohci_usb_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-ohci", },
 	{ .compatible = "allwinner,sun7i-a20-ohci", },
 	{ .compatible = "allwinner,sun8i-a23-ohci", },
+	{ .compatible = "allwinner,sun8i-h3-ohci",  },
 	{ .compatible = "allwinner,sun9i-a80-ohci", },
 	{ }
 };
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 781ff6eae2..7c0ab1eab4 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -18,7 +18,11 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #endif
 
-#define CONFIG_SUNXI_USB_PHYS	2
+#ifdef CONFIG_MACH_SUN8I_H3
+	#define CONFIG_SUNXI_USB_PHYS	4
+#else
+	#define CONFIG_SUNXI_USB_PHYS	2
+#endif
 
 
 #ifndef CONFIG_MACH_SUN8I_A83T
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b4dfb3cc47..40850e5d99 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -206,7 +206,8 @@
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 /* I2C */
-#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
+    defined CONFIG_SY8106A_POWER
 #define CONFIG_SPL_I2C_SUPPORT
 #endif
 
@@ -240,7 +241,8 @@ extern int soft_i2c_gpio_scl;
 
 /* PMU */
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
-    defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+    defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \
+    defined CONFIG_SY8106A_POWER
 #define CONFIG_SPL_POWER_SUPPORT
 #endif
 
diff --git a/include/sy8106a.h b/include/sy8106a.h
new file mode 100644
index 0000000000..32e8c43dc0
--- /dev/null
+++ b/include/sy8106a.h
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2016
+ * Jelle van der Waa <jelle@vdwaa.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SY8106A_PMIC_H_
+
+int sy8106a_set_vout1(unsigned int mvolt);
+
+#endif