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authorPeng Fan <peng.fan@nxp.com>2016-11-22 19:41:09 +0800
committerTom Rini <trini@konsulko.com>2016-11-29 08:15:31 -0500
commitfea7452c15081127e07b77e286a89d2c296f6b05 (patch)
tree4d350ec55778ab7d7cd8159ce9b3bb9c24e45665 /.travis.yml
parent88e0d59315f4863537a94f12ef48348764f4316b (diff)
armv7: psci: cpu_off: flush D-Cache before disable D-Cache
Before disable cache, need to first flush cache. There maybe dirty data in D-Cache before disable D-Cache. After disable D-Cache, the first store instructions in psci_v7_flush_dcache_all will directly store registers {r4-r5, r7, r9-r11, lr} to memory. If there is dirty data before disable D-Cache, psci_v7_flush_dcache_all will flush data to memory, and may overwrite the memory that hold the registers {r4-r5, r7, r9-r11, lr}. So before disable cache, first flush D-Cache. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Tom Rini <trini@konsulko.com>
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