From 167a935733a6e3e412b8ed6a60034d0d84895f2e Mon Sep 17 00:00:00 2001 From: Andrew Thoelke Date: Wed, 4 Jun 2014 21:10:52 +0100 Subject: Initialise CPU contexts from entry_point_info Consolidate all BL3-1 CPU context initialization for cold boot, PSCI and SPDs into two functions: * The first uses entry_point_info to initialize the relevant cpu_context for first entry into a lower exception level on a CPU * The second populates the EL1 and EL2 system registers as needed from the cpu_context to ensure correct entry into the lower EL This patch alters the way that BL3-1 determines which exception level is used when first entering EL1 or EL2 during cold boot - this is now fully determined by the SPSR value in the entry_point_info for BL3-3, as set up by the platform code in BL2 (or otherwise provided to BL3-1). In the situation that EL1 (or svc mode) is selected for a processor that supports EL2, the context management code will now configure all essential EL2 register state to ensure correct execution of EL1. This allows the platform code to run non-secure EL1 payloads directly without requiring a small EL2 stub or OS loader. Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f --- services/std_svc/psci/psci_afflvl_off.c | 8 +- services/std_svc/psci/psci_afflvl_on.c | 17 ++-- services/std_svc/psci/psci_afflvl_suspend.c | 21 +++-- services/std_svc/psci/psci_common.c | 138 ++++++---------------------- services/std_svc/psci/psci_private.h | 24 +---- services/std_svc/psci/psci_setup.c | 2 +- 6 files changed, 55 insertions(+), 155 deletions(-) (limited to 'services/std_svc') diff --git a/services/std_svc/psci/psci_afflvl_off.c b/services/std_svc/psci/psci_afflvl_off.c index 21a4d1a..30f2bd1 100644 --- a/services/std_svc/psci/psci_afflvl_off.c +++ b/services/std_svc/psci/psci_afflvl_off.c @@ -42,8 +42,8 @@ typedef int (*afflvl_off_handler_t)(unsigned long, aff_map_node_t *); ******************************************************************************/ static int psci_afflvl0_off(unsigned long mpidr, aff_map_node_t *cpu_node) { - unsigned int index, plat_state; - int rc = PSCI_E_SUCCESS; + unsigned int plat_state; + int rc; unsigned long sctlr; assert(cpu_node->level == MPIDR_AFFLVL0); @@ -67,9 +67,6 @@ static int psci_afflvl0_off(unsigned long mpidr, aff_map_node_t *cpu_node) return rc; } - index = cpu_node->data; - memset(&psci_ns_entry_info[index], 0, sizeof(psci_ns_entry_info[index])); - /* * Arch. management. Perform the necessary steps to flush all * cpu caches. @@ -96,6 +93,7 @@ static int psci_afflvl0_off(unsigned long mpidr, aff_map_node_t *cpu_node) * Plat. management: Perform platform specific actions to turn this * cpu off e.g. exit cpu coherency, program the power controller etc. */ + rc = PSCI_E_SUCCESS; if (psci_plat_pm_ops->affinst_off) { /* Get the current physical state of this cpu */ diff --git a/services/std_svc/psci/psci_afflvl_on.c b/services/std_svc/psci/psci_afflvl_on.c index e4d8f1f..d91db96 100644 --- a/services/std_svc/psci/psci_afflvl_on.c +++ b/services/std_svc/psci/psci_afflvl_on.c @@ -75,8 +75,10 @@ static int psci_afflvl0_on(unsigned long target_cpu, unsigned long ns_entrypoint, unsigned long context_id) { - unsigned int index, plat_state; + unsigned int plat_state; unsigned long psci_entrypoint; + uint32_t ns_scr_el3 = read_scr_el3(); + uint32_t ns_sctlr_el1 = read_sctlr_el1(); int rc; /* Sanity check to safeguard against data corruption */ @@ -103,8 +105,8 @@ static int psci_afflvl0_on(unsigned long target_cpu, * the non-secure world from the non-secure state from * where this call originated. */ - index = cpu_node->data; - rc = psci_set_ns_entry_info(index, ns_entrypoint, context_id); + rc = psci_save_ns_entry(target_cpu, ns_entrypoint, context_id, + ns_scr_el3, ns_sctlr_el1); if (rc != PSCI_E_SUCCESS) return rc; @@ -336,7 +338,7 @@ int psci_afflvl_on(unsigned long target_cpu, static unsigned int psci_afflvl0_on_finish(unsigned long mpidr, aff_map_node_t *cpu_node) { - unsigned int index, plat_state, state, rc = PSCI_E_SUCCESS; + unsigned int plat_state, state, rc; assert(cpu_node->level == MPIDR_AFFLVL0); @@ -383,11 +385,9 @@ static unsigned int psci_afflvl0_on_finish(unsigned long mpidr, /* * Generic management: Now we just need to retrieve the * information that we had stashed away during the cpu_on - * call to set this cpu on its way. First get the index - * for restoring the re-entry info + * call to set this cpu on its way. */ - index = cpu_node->data; - psci_get_ns_entry_info(index); + cm_prepare_el3_exit(NON_SECURE); /* State management: mark this cpu as on */ psci_set_state(cpu_node, PSCI_STATE_ON); @@ -395,6 +395,7 @@ static unsigned int psci_afflvl0_on_finish(unsigned long mpidr, /* Clean caches before re-entering normal world */ dcsw_op_louis(DCCSW); + rc = PSCI_E_SUCCESS; return rc; } diff --git a/services/std_svc/psci/psci_afflvl_suspend.c b/services/std_svc/psci/psci_afflvl_suspend.c index 9934310..f43dced 100644 --- a/services/std_svc/psci/psci_afflvl_suspend.c +++ b/services/std_svc/psci/psci_afflvl_suspend.c @@ -132,10 +132,12 @@ static int psci_afflvl0_suspend(unsigned long mpidr, unsigned long context_id, unsigned int power_state) { - unsigned int index, plat_state; + unsigned int plat_state; unsigned long psci_entrypoint, sctlr; el3_state_t *saved_el3_state; - int rc = PSCI_E_SUCCESS; + uint32_t ns_scr_el3 = read_scr_el3(); + uint32_t ns_sctlr_el1 = read_sctlr_el1(); + int rc; /* Sanity check to safeguard against data corruption */ assert(cpu_node->level == MPIDR_AFFLVL0); @@ -163,8 +165,8 @@ static int psci_afflvl0_suspend(unsigned long mpidr, * Generic management: Store the re-entry information for the * non-secure world */ - index = cpu_node->data; - rc = psci_set_ns_entry_info(index, ns_entrypoint, context_id); + rc = psci_save_ns_entry(read_mpidr_el1(), ns_entrypoint, context_id, + ns_scr_el3, ns_sctlr_el1); if (rc != PSCI_E_SUCCESS) return rc; @@ -174,7 +176,6 @@ static int psci_afflvl0_suspend(unsigned long mpidr, * L1 caches and exit intra-cluster coherency et al */ cm_el3_sysregs_context_save(NON_SECURE); - rc = PSCI_E_SUCCESS; /* * The EL3 state to PoC since it will be accessed after a @@ -214,6 +215,8 @@ static int psci_afflvl0_suspend(unsigned long mpidr, * platform defined mailbox with the psci entrypoint, * program the power controller etc. */ + rc = PSCI_E_SUCCESS; + if (psci_plat_pm_ops->affinst_suspend) { plat_state = psci_get_phys_state(cpu_node); rc = psci_plat_pm_ops->affinst_suspend(mpidr, @@ -454,7 +457,7 @@ int psci_afflvl_suspend(unsigned long mpidr, static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr, aff_map_node_t *cpu_node) { - unsigned int index, plat_state, state, rc = PSCI_E_SUCCESS; + unsigned int plat_state, state, rc; int32_t suspend_level; assert(cpu_node->level == MPIDR_AFFLVL0); @@ -481,14 +484,11 @@ static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr, } /* Get the index for restoring the re-entry information */ - index = cpu_node->data; - /* * Arch. management: Restore the stashed EL3 architectural * context from the 'cpu_context' structure for this cpu. */ cm_el3_sysregs_context_restore(NON_SECURE); - rc = PSCI_E_SUCCESS; /* * Call the cpu suspend finish handler registered by the Secure Payload @@ -509,7 +509,7 @@ static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr, * information that we had stashed away during the suspend * call to set this cpu on its way. */ - psci_get_ns_entry_info(index); + cm_prepare_el3_exit(NON_SECURE); /* State management: mark this cpu as on */ psci_set_state(cpu_node, PSCI_STATE_ON); @@ -517,6 +517,7 @@ static unsigned int psci_afflvl0_suspend_finish(unsigned long mpidr, /* Clean caches before re-entering normal world */ dcsw_op_louis(DCCSW); + rc = PSCI_E_SUCCESS; return rc; } diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c index 3cbacd7..d69c5f5 100644 --- a/services/std_svc/psci/psci_common.c +++ b/services/std_svc/psci/psci_common.c @@ -36,6 +36,7 @@ #include #include #include +#include #include "psci_private.h" /* @@ -50,7 +51,6 @@ const spd_pm_ops_t *psci_spd_pm; * array during startup. ******************************************************************************/ suspend_context_t psci_suspend_context[PSCI_NUM_AFFS]; -ns_entry_info_t psci_ns_entry_info[PSCI_NUM_AFFS]; /******************************************************************************* * Grand array that holds the platform's topology information for state @@ -212,97 +212,36 @@ int psci_validate_mpidr(unsigned long mpidr, int level) } /******************************************************************************* - * This function retrieves all the stashed information needed to correctly - * resume a cpu's execution in the non-secure state after it has been physically - * powered on i.e. turned ON or resumed from SUSPEND + * This function determines the full entrypoint information for the requested + * PSCI entrypoint on power on/resume and saves this in the non-secure CPU + * cpu_context, ready for when the core boots. ******************************************************************************/ -void psci_get_ns_entry_info(unsigned int index) +int psci_save_ns_entry(uint64_t mpidr, + uint64_t entrypoint, uint64_t context_id, + uint32_t ns_scr_el3, uint32_t ns_sctlr_el1) { - unsigned long sctlr = 0, scr, el_status, id_aa64pfr0; - cpu_context_t *ns_entry_context; - gp_regs_t *ns_entry_gpregs; + uint32_t ep_attr, mode, sctlr, daif, ee; + entry_point_info_t ep; - scr = read_scr(); + sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1; + ee = 0; - /* Find out which EL we are going to */ - id_aa64pfr0 = read_id_aa64pfr0_el1(); - el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) & - ID_AA64PFR0_ELX_MASK; - - /* Restore endianess */ - if (psci_ns_entry_info[index].sctlr & SCTLR_EE_BIT) - sctlr |= SCTLR_EE_BIT; - else - sctlr &= ~SCTLR_EE_BIT; - - /* Turn off MMU and Caching */ - sctlr &= ~(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_M_BIT); - - /* Set the register width */ - if (psci_ns_entry_info[index].scr & SCR_RW_BIT) - scr |= SCR_RW_BIT; - else - scr &= ~SCR_RW_BIT; - - scr |= SCR_NS_BIT; - - if (el_status) - write_sctlr_el2(sctlr); - else - write_sctlr_el1(sctlr); - - /* Fulfill the cpu_on entry reqs. as per the psci spec */ - ns_entry_context = (cpu_context_t *) cm_get_context(NON_SECURE); - assert(ns_entry_context); - - /* - * Setup general purpose registers to return the context id and - * prevent leakage of secure information into the normal world. - */ - ns_entry_gpregs = get_gpregs_ctx(ns_entry_context); - write_ctx_reg(ns_entry_gpregs, - CTX_GPREG_X0, - psci_ns_entry_info[index].context_id); - - /* - * Tell the context management library to setup EL3 system registers to - * be able to ERET into the ns state, and SP_EL3 points to the right - * context to exit from EL3 correctly. - */ - cm_set_el3_eret_context(NON_SECURE, - psci_ns_entry_info[index].eret_info.entrypoint, - psci_ns_entry_info[index].eret_info.spsr, - scr); - - cm_set_next_eret_context(NON_SECURE); -} - -/******************************************************************************* - * This function retrieves and stashes all the information needed to correctly - * resume a cpu's execution in the non-secure state after it has been physically - * powered on i.e. turned ON or resumed from SUSPEND. This is done prior to - * turning it on or before suspending it. - ******************************************************************************/ -int psci_set_ns_entry_info(unsigned int index, - unsigned long entrypoint, - unsigned long context_id) -{ - int rc = PSCI_E_SUCCESS; - unsigned int rw, mode, ee, spsr = 0; - unsigned long id_aa64pfr0 = read_id_aa64pfr0_el1(), scr = read_scr(); - unsigned long el_status; - unsigned long daif; + ep_attr = NON_SECURE | EP_ST_DISABLE; + if (sctlr & SCTLR_EE_BIT) { + ep_attr |= EP_EE_BIG; + ee = 1; + } + SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1, ep_attr); - /* Figure out what mode do we enter the non-secure world in */ - el_status = (id_aa64pfr0 >> ID_AA64PFR0_EL2_SHIFT) & - ID_AA64PFR0_ELX_MASK; + ep.pc = entrypoint; + memset(&ep.args, 0, sizeof(ep.args)); + ep.args.arg0 = context_id; /* * Figure out whether the cpu enters the non-secure address space * in aarch32 or aarch64 */ - rw = scr & SCR_RW_BIT; - if (rw) { + if (ns_scr_el3 & SCR_RW_BIT) { /* * Check whether a Thumb entry point has been provided for an @@ -311,28 +250,12 @@ int psci_set_ns_entry_info(unsigned int index, if (entrypoint & 0x1) return PSCI_E_INVALID_PARAMS; - if (el_status && (scr & SCR_HCE_BIT)) { - mode = MODE_EL2; - ee = read_sctlr_el2() & SCTLR_EE_BIT; - } else { - mode = MODE_EL1; - ee = read_sctlr_el1() & SCTLR_EE_BIT; - } - - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1; - psci_ns_entry_info[index].sctlr |= ee; - psci_ns_entry_info[index].scr |= SCR_RW_BIT; + ep.spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } else { - - if (el_status && (scr & SCR_HCE_BIT)) { - mode = MODE32_hyp; - ee = read_sctlr_el2() & SCTLR_EE_BIT; - } else { - mode = MODE32_svc; - ee = read_sctlr_el1() & SCTLR_EE_BIT; - } + mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; /* * TODO: Choose async. exception bits if HYP mode is not @@ -340,18 +263,13 @@ int psci_set_ns_entry_info(unsigned int index, */ daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; - spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); - - /* Ensure that the CSPR.E and SCTLR.EE bits match */ - psci_ns_entry_info[index].sctlr |= ee; - psci_ns_entry_info[index].scr &= ~SCR_RW_BIT; + ep.spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); } - psci_ns_entry_info[index].eret_info.entrypoint = entrypoint; - psci_ns_entry_info[index].eret_info.spsr = spsr; - psci_ns_entry_info[index].context_id = context_id; + /* initialise an entrypoint to set up the CPU context */ + cm_init_context(mpidr, &ep); - return rc; + return PSCI_E_SUCCESS; } /******************************************************************************* diff --git a/services/std_svc/psci/psci_private.h b/services/std_svc/psci/psci_private.h index 747a2d4..970ad21 100644 --- a/services/std_svc/psci/psci_private.h +++ b/services/std_svc/psci/psci_private.h @@ -35,22 +35,6 @@ #include #include -/******************************************************************************* - * The following two data structures hold the generic information to bringup - * a suspended/hotplugged out cpu - ******************************************************************************/ -typedef struct eret_params { - unsigned long entrypoint; - unsigned long spsr; -} eret_params_t; - -typedef struct ns_entry_info { - eret_params_t eret_info; - unsigned long context_id; - unsigned int scr; - unsigned int sctlr; -} ns_entry_info_t; - /******************************************************************************* * The following two data structures hold the topology tree which in turn tracks * the state of the all the affinity instances supported by the platform. @@ -85,7 +69,6 @@ typedef unsigned int (*afflvl_power_on_finisher_t)(unsigned long, * Data prototypes ******************************************************************************/ extern suspend_context_t psci_suspend_context[PSCI_NUM_AFFS]; -extern ns_entry_info_t psci_ns_entry_info[PSCI_NUM_AFFS]; extern const plat_pm_ops_t *psci_plat_pm_ops; extern aff_map_node_t psci_aff_map[PSCI_NUM_AFFS]; @@ -102,7 +85,6 @@ int get_max_afflvl(void); unsigned short psci_get_state(aff_map_node_t *node); unsigned short psci_get_phys_state(aff_map_node_t *node); void psci_set_state(aff_map_node_t *node, unsigned short state); -void psci_get_ns_entry_info(unsigned int index); unsigned long mpidr_set_aff_inst(unsigned long, unsigned char, int); int psci_validate_mpidr(unsigned long, int); int get_power_on_target_afflvl(unsigned long mpidr); @@ -110,9 +92,9 @@ void psci_afflvl_power_on_finish(unsigned long, int, int, afflvl_power_on_finisher_t *); -int psci_set_ns_entry_info(unsigned int index, - unsigned long entrypoint, - unsigned long context_id); +int psci_save_ns_entry(uint64_t mpidr, + uint64_t entrypoint, uint64_t context_id, + uint32_t caller_scr_el3, uint32_t caller_sctlr_el1); int psci_check_afflvl_range(int start_afflvl, int end_afflvl); void psci_acquire_afflvl_locks(unsigned long mpidr, int start_afflvl, diff --git a/services/std_svc/psci/psci_setup.c b/services/std_svc/psci/psci_setup.c index 015beab..af82150 100644 --- a/services/std_svc/psci/psci_setup.c +++ b/services/std_svc/psci/psci_setup.c @@ -59,7 +59,7 @@ static aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1]; /******************************************************************************* * 'psci_ns_einfo_idx' keeps track of the next free index in the - * 'psci_ns_entry_info' & 'psci_suspend_context' arrays. + * 'psci_suspend_context' arrays. ******************************************************************************/ static unsigned int psci_ns_einfo_idx; -- cgit v1.2.3