From 633933c3d56932e6ddb54bcc2ac904f3fec206d3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 2 May 2016 00:50:00 +0100 Subject: sun50i: add OpenRISC stop code near BL31 start point As ATF is now disguised as the SCP, eventually boot0 will power on the arisc and it will try to let it execute OpenRISC code. Provide some OpenRISC code to shut the core down again, by setting the shutdown bit in the PMR special register. The code sequence is: l.xor r0, r0, r0 ; clear r0 l.ori r1, r0, 0xc0 ; r1 = 0xc0 l.mtspr r0, r1, 0x4000 ; PMR(@0x4000) := r1 (0x40) Signed-off-by: Andre Przywara --- bl31/aarch64/bl31_entrypoint.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 6f5a7c0..8e10d6a 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -41,12 +41,21 @@ * ----------------------------------------------------- */ func bl31_entrypoint + b code_start + nop /* align to 8 bytes */ + .byte 0x05, 0x00, 0x00, 0xe0, 0x00, 0x04, 0x02, 0xa8 + /* l.xor r0, r0, r0 l.ori r1, r0, 0xc0 */ + .byte 0x00, 0x80, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x15 + /* l.mtspr r0, r1, 0x4000 l.nop */ + /* --------------------------------------------------------------- * Preceding bootloader has populated x0 with a pointer to a * 'bl31_params' structure & x1 with a pointer to platform * specific structure * --------------------------------------------------------------- */ + +code_start: #if !RESET_TO_BL31 /* *AA32 warmreset to AA64, the high 32bit in reg R0,R1 is unpredictable -- cgit v1.2.3