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-rw-r--r--plat/sun50iw1p1/bl31_sunxi_setup.c8
-rw-r--r--plat/sun50iw1p1/sunxi_clocks.c8
-rw-r--r--plat/sun50iw1p1/sunxi_private.h2
3 files changed, 14 insertions, 4 deletions
diff --git a/plat/sun50iw1p1/bl31_sunxi_setup.c b/plat/sun50iw1p1/bl31_sunxi_setup.c
index 607bce0..d69a079 100644
--- a/plat/sun50iw1p1/bl31_sunxi_setup.c
+++ b/plat/sun50iw1p1/bl31_sunxi_setup.c
@@ -235,16 +235,20 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
******************************************************************************/
void bl31_platform_setup(void)
{
+ uint16_t socid;
+
/* Initialize the gic cpu and distributor interfaces */
arm_gic_init(GICC_BASE, GICD_BASE, 0, NULL, 0);
arm_gic_setup();
+ socid = sunxi_get_socid();
+
/* Detect if this SoC is a multi-cluster one. */
plat_setup_topology();
- sunxi_setup_clocks();
+ sunxi_setup_clocks(socid);
- switch (sunxi_get_socid()) {
+ switch (socid) {
case 0x1689:
sunxi_pmic_setup();
break;
diff --git a/plat/sun50iw1p1/sunxi_clocks.c b/plat/sun50iw1p1/sunxi_clocks.c
index 9a0b174..a071024 100644
--- a/plat/sun50iw1p1/sunxi_clocks.c
+++ b/plat/sun50iw1p1/sunxi_clocks.c
@@ -33,7 +33,7 @@
#include <ccmu.h>
#include "sunxi_private.h"
-int sunxi_setup_clocks(void)
+int sunxi_setup_clocks(uint16_t socid)
{
uint32_t reg;
@@ -44,6 +44,8 @@ int sunxi_setup_clocks(void)
/* Check initial CPU frequency: */
reg = mmio_read_32(CCMU_PLL_CPUX_CTRL_REG);
+
+ if (socid == 0x1689) {
if ((reg & 0x0fffffff) != 0x1010) { /* if not at 816 MHz: */
/* switch CPU to 24 MHz source for changing PLL1 */
mmio_write_32(CCMU_CPUX_AXI_CFG_REG, 0x00010000);
@@ -58,6 +60,10 @@ int sunxi_setup_clocks(void)
mmio_write_32(CCMU_CPUX_AXI_CFG_REG, 0x00020302);
udelay(1);
+ } else {
+ NOTICE("PLL_CPUX: %x\n", reg);
+ }
+
/* AHB1 = PERIPH0 / (3 * 1) = 200MHz, APB1 = AHB1 / 2 */
mmio_write_32(CCMU_AHB1_APB1_CFG_REG, 0x00003180);
mmio_write_32(CCMU_APB2_CFG_GREG, 0x01000000); /* APB2 => 24 MHz */
diff --git a/plat/sun50iw1p1/sunxi_private.h b/plat/sun50iw1p1/sunxi_private.h
index 6f1f637..aefa763 100644
--- a/plat/sun50iw1p1/sunxi_private.h
+++ b/plat/sun50iw1p1/sunxi_private.h
@@ -73,7 +73,7 @@ int sunxi_pmic_read(uint8_t address);
int sunxi_pmic_write(uint8_t address, uint8_t value);
void udelay(unsigned int delay);
-int sunxi_setup_clocks(void);
+int sunxi_setup_clocks(uint16_t socid);
/* Gets the SPSR for BL33 entry */
uint32_t sunxi_get_spsr_for_bl33_entry(int aarch);