diff options
| -rw-r--r-- | plat/sun50iw1p1/sunxi_clocks.c | 28 | ||||
| -rw-r--r-- | plat/sun50iw1p1/sunxi_private.h | 1 |
2 files changed, 27 insertions, 2 deletions
diff --git a/plat/sun50iw1p1/sunxi_clocks.c b/plat/sun50iw1p1/sunxi_clocks.c index ac7a314..e404d19 100644 --- a/plat/sun50iw1p1/sunxi_clocks.c +++ b/plat/sun50iw1p1/sunxi_clocks.c @@ -94,8 +94,6 @@ void sun50i_set_cpu_pll(unsigned int freq_mhz) uint8_t n, k, m; uint32_t reg; - NOTICE("BL3-1: Reprogramming clocks for %d MHz\n", freq_mhz); - /* Set up dividers (suitable for the target clock frequency) and switch CPUX (and thus AXI & APB) to the LOSC24 clock */ mmio_write_32(CCMU_CPUX_AXI_CFG_REG, ( CPUX_SRCSEL_OSC24M | @@ -128,6 +126,32 @@ void sun50i_set_cpu_pll(unsigned int freq_mhz) udelay(1000); } +unsigned int sun50i_get_cpu_pll(void) +{ + uint8_t k, m, n, p; + uint32_t reg; + + /* Read out the PLL CPUX control register */ + reg = mmio_read_32(CCMU_PLL_CPUX_CTRL_REG); + + /* Parse the PLL factors */ + p = (reg>>16) & 0x3; + n = (reg>>8) & 0xff; + k = (reg>>4) & 0x3; + m = reg & 0x3; + + /* Transform p to a divider */ + if (p == 0) + p = 1; + else if (p == 1) + p = 2; + else + p = 4; + + /* Return the PLL frequency in MHz. */ + return 24*(n+1)*(k+1)/((m+1)*p); +} + int sunxi_setup_clocks(uint16_t socid) { uint32_t reg; diff --git a/plat/sun50iw1p1/sunxi_private.h b/plat/sun50iw1p1/sunxi_private.h index 116a38b..4750056 100644 --- a/plat/sun50iw1p1/sunxi_private.h +++ b/plat/sun50iw1p1/sunxi_private.h @@ -75,6 +75,7 @@ int sunxi_pmic_write(uint8_t address, uint8_t value); void udelay(unsigned int delay); int sunxi_setup_clocks(uint16_t socid); void sun50i_set_cpu_pll(unsigned int freq_mhz); +unsigned int sun50i_get_cpu_pll(void); /* Gets the SPSR for BL33 entry */ uint32_t sunxi_get_spsr_for_bl33_entry(int aarch); |