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authorAndre Przywara <andre.przywara@arm.com>2016-08-10 01:16:36 +0100
committerAndre Przywara <andre.przywara@arm.com>2016-10-23 10:59:51 +0100
commite70dd6ebe65d62d4d4d5873c3d2c900fe5633313 (patch)
tree404c862235e5e5a8a34324fb697d55d3ccfc7e79 /plat/sun50iw1p1
parent4409b3959edf7fd41707f773640e74fdef096383 (diff)
sunxi: setup basic clocks
Different ways of booting set up the clocks differently, so lets initialize the basic clocks here to be on the same page.
Diffstat (limited to 'plat/sun50iw1p1')
-rw-r--r--plat/sun50iw1p1/bl31_sunxi_setup.c1
-rw-r--r--plat/sun50iw1p1/platform.mk1
-rw-r--r--plat/sun50iw1p1/sunxi_clocks.c67
-rw-r--r--plat/sun50iw1p1/sunxi_private.h3
4 files changed, 72 insertions, 0 deletions
diff --git a/plat/sun50iw1p1/bl31_sunxi_setup.c b/plat/sun50iw1p1/bl31_sunxi_setup.c
index 0f2eff8..16b27d7 100644
--- a/plat/sun50iw1p1/bl31_sunxi_setup.c
+++ b/plat/sun50iw1p1/bl31_sunxi_setup.c
@@ -228,6 +228,7 @@ void bl31_platform_setup(void)
/* Detect if this SoC is a multi-cluster one. */
plat_setup_topology();
+ sunxi_setup_clocks();
sunxi_pmic_setup();
}
diff --git a/plat/sun50iw1p1/platform.mk b/plat/sun50iw1p1/platform.mk
index 4fa5098..34fa2b1 100644
--- a/plat/sun50iw1p1/platform.mk
+++ b/plat/sun50iw1p1/platform.mk
@@ -51,5 +51,6 @@ BL31_SOURCES += drivers/arm/gic/arm_gic.c \
plat/sun50iw1p1/sunxi_cpu_ops.c \
plat/sun50iw1p1/plat_topology.c \
plat/sun50iw1p1/aarch64/plat_helpers.S \
+ plat/sun50iw1p1/sunxi_clocks.c \
plat/sun50iw1p1/aarch64/sunxi_common.c
diff --git a/plat/sun50iw1p1/sunxi_clocks.c b/plat/sun50iw1p1/sunxi_clocks.c
new file mode 100644
index 0000000..9a0b174
--- /dev/null
+++ b/plat/sun50iw1p1/sunxi_clocks.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <mmio.h>
+#include <ccmu.h>
+#include "sunxi_private.h"
+
+int sunxi_setup_clocks(void)
+{
+ uint32_t reg;
+
+ /* Avoid reprogramming PERIPH0 if not necessary */
+ reg = mmio_read_32(CCMU_PLL_PERIPH0_CTRL_REG);
+ if ((reg & 0x0fffffff) != 0x41811) /* is not at 600 MHz? */
+ mmio_write_32(CCMU_PLL_PERIPH0_CTRL_REG, 0x80041811);
+
+ /* Check initial CPU frequency: */
+ reg = mmio_read_32(CCMU_PLL_CPUX_CTRL_REG);
+ if ((reg & 0x0fffffff) != 0x1010) { /* if not at 816 MHz: */
+ /* switch CPU to 24 MHz source for changing PLL1 */
+ mmio_write_32(CCMU_CPUX_AXI_CFG_REG, 0x00010000);
+ udelay(1);
+
+ /* Set to 816 MHz */
+ mmio_write_32(CCMU_PLL_CPUX_CTRL_REG, 0x80001010);
+ udelay(1);
+ }
+
+ /* switch CPU to PLL1 source, AXI = CPU/3, APB = CPU/4 */
+ mmio_write_32(CCMU_CPUX_AXI_CFG_REG, 0x00020302);
+ udelay(1);
+
+ /* AHB1 = PERIPH0 / (3 * 1) = 200MHz, APB1 = AHB1 / 2 */
+ mmio_write_32(CCMU_AHB1_APB1_CFG_REG, 0x00003180);
+ mmio_write_32(CCMU_APB2_CFG_GREG, 0x01000000); /* APB2 => 24 MHz */
+ mmio_write_32(CCMU_AHB2_CFG_GREG, 0x00000001); /* AHB2 => 300 MHz */
+
+ return 0;
+}
diff --git a/plat/sun50iw1p1/sunxi_private.h b/plat/sun50iw1p1/sunxi_private.h
index cfc7ff8..c41c431 100644
--- a/plat/sun50iw1p1/sunxi_private.h
+++ b/plat/sun50iw1p1/sunxi_private.h
@@ -70,6 +70,9 @@ int sunxi_pmic_setup(void);
int sunxi_pmic_read(uint8_t address);
int sunxi_pmic_write(uint8_t address, uint8_t value);
+void udelay(unsigned int delay);
+int sunxi_setup_clocks(void);
+
/* Gets the SPSR for BL33 entry */
uint32_t sunxi_get_spsr_for_bl33_entry(int aarch);