diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-01-30 17:54:17 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-02-02 23:58:14 +0100 |
| commit | 2c07579f82399b067de5f3b7650dc09d633e3a11 (patch) | |
| tree | d6237dba86d4a1e122bbbcec031377f95113306a /plat/sun50iw1p1 | |
| parent | e0d77b508aaf5fe833df755097959dd98053d0e0 (diff) | |
sun50iw1p1: Adjust PMIC setting for the A64-uQ7 (DDR3L and GbE PHY)
For the A64-uQ7 we should set up DCDC5 (DDR) to 1.36V and DCDC4 to 1.2V
(for the Micrel GbE PHY). Note that a higher DCDC5 setting (i.e. 1.5V)
will also work safely, but we expect a power-saving under high system load
from using the lower DDR3L voltage supported by our RAM.
Per my discussion with Andre, board-specific power initialisation should
eventually be conditionalised on the FDT, as seen by the ATF. However,
this will require the ATF to be rebased to a more current ATF source
bae first.
X-AffectedPlatforms: A64-uQ7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'plat/sun50iw1p1')
| -rw-r--r-- | plat/sun50iw1p1/sunxi_power.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/plat/sun50iw1p1/sunxi_power.c b/plat/sun50iw1p1/sunxi_power.c index 11badcd..9ab605e 100644 --- a/plat/sun50iw1p1/sunxi_power.c +++ b/plat/sun50iw1p1/sunxi_power.c @@ -251,7 +251,12 @@ static int pmic_setup(void) } } - sunxi_pmic_write(0x24, 0xb3); /* DCDC5 = DDR RAM voltage = 1.5V */ + ret = sunxi_pmic_read(0x10); + sunxi_pmic_write(0x10, ret | (1 << 3)); + + sunxi_pmic_write(0x23, 0x46); /* DCDC4 = ETH PHY = 1.2V */ + sunxi_pmic_write(0x24, 0x2c); /* DCDC5 = DDR3L voltage = 1.36V */ + // sunxi_pmic_write(0x24, 0xb3); /* DCDC5 = DDR RAM voltage = 1.5V */ return 0; } |