diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2016-04-24 23:40:34 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2016-06-02 01:29:48 +0100 |
| commit | ea17218134b77ee7bab3091984944fd4070924af (patch) | |
| tree | c3d0f1bfb190dd9aabfdf094e16f6620f298d54a | |
| parent | 176571f482d96629e314dad44673a7492ffd3cfa (diff) | |
lib/aarch64: remove dead code for MMU tables
Remove pointless (because commented) code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | lib/aarch64/xlat_tables.c | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c index 82ae898..709a778 100644 --- a/lib/aarch64/xlat_tables.c +++ b/lib/aarch64/xlat_tables.c @@ -349,58 +349,3 @@ DEFINE_ENABLE_MMU_EL(1, DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT), tlbialle3) - -#if 0 -void enable_mmu_el3(uint32_t flags) -{ - uint64_t mair, tcr, ttbr; - uint32_t sctlr; - uint32_t _tcr_extra = TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); - - - assert(IS_IN_EL(_el)); - assert((read_sctlr_el3() & SCTLR_M_BIT) == 0); - - /* Set attributes in the right indices of the MAIR */ - mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); - mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, - ATTR_IWBWA_OWBWA_NTR_INDEX); - write_mair_el3(mair); - - /* Invalidate TLBs at the current exception level */ - tlbialle3(); - - /* Set TCR bits as well. */ - /* Inner & outer WBWA & shareable + T0SZ = 32 */ - tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | - TCR_RGN_INNER_WBA | - (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); - tcr |= _tcr_extra; - write_tcr_el3(tcr); - - /* Set TTBR bits as well */ - ttbr = (uint64_t) l1_xlation_table; - write_ttbr0_el3(ttbr); - - /* Ensure all translation table writes have drained */ - /* into memory, the TLB invalidation is complete, */ - /* and translation register writes are committed */ - /* before enabling the MMU */ - dsb(); - isb(); - - sctlr = read_sctlr_el3(); - sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; - - if (flags & DISABLE_DCACHE) - sctlr &= ~SCTLR_C_BIT; - else - sctlr |= SCTLR_C_BIT; - - write_sctlr_el3(sctlr); - - /* Ensure the MMU enable takes effect immediately */ - isb(); -} -#endif - |