summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2017-10-02arm: mark save_boot_params_ret as a functionPhilipp Tomsich
As no '.type' was set for save_boot_params_ret in start.S, binutils did not track whether it was emitted as A32 or T32. By properly marking save_boot_params_ret as a potential function entry, we can make sure that the compiler will insert the appropriate instructions for branching to save_boot_params_ret both for call-sites emitted as A32 and T32. Reported-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com> Series-changes: 3 - tracked the root-cause why no interwork branch was emitted and fixed it using a '.type'-directive in start.S to mark save_boot_params_ret as a (possible) function-entry.
2017-10-02arm: make save_boot_params_ret prototype visible for AArch64Philipp Tomsich
The save_boot_params_ret() prototype (for those of us, that have a valid SP on entry and can implement save_boot_params() in C), was previously only defined for !defined(CONFIG_ARM64). This moves the declaration to a common block to ensure the prototype is available to everyone that might need it. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2017-10-02rockchip: dts: rk3399-puma: add /config/arm-trusted-firmware,reset-gpio propertyPhilipp Tomsich
With the ATF capable of accessing the FDT passed to the next stage, we can specify configuration items for the ATF in the /config path. This adds the arm-trusted-firmware,reset-gpio that conveys the number of the GPIO used to reset the board (used, when a reboot is requested from ATF via PSCI). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: enable TPL_SYSRESET for all rockchip SoCsKever Yang
With Makefiles testing for $(SPL_TPL_)SYSRESET, we need TPL_SYSRESET for do_reset() in TPL for Rockchip SoCs. References: 87c16d4 "drivers: spl: consistently use the $(SPL_TPL_) macro" Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rk3288: spl: Add dram_init_banksizeJagan Teki
Falcon mode, is updating DDR dt node configuration through spl_fixup_fdt() so add appropriate DDR base and size through dram_init_banksize. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3399-puma: add boot-on regulator to override BIOS_DISABLEPhilipp Tomsich
The (Qseven) BIOS_DISABLE signal on the RK3399-Q7 (Puma) keeps the eMMC and SPI in reset initially and we need to write a GPIO to turn them on before continuing the boot-up. This adds the DTS entries for the additional regulator and makes pinctrl and gpio3 available during SPL. It also adds a hook to the spl_board_init() to ensure that the regulator gets probed and enabled. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: dts: rk3399-puma: add 'same-as-spl' to the front of the boot-orderPhilipp Tomsich
In the general case, we want to continue booting the full U-Boot (contained in a discoverable FIT image) from the same device the SPL stage was loaded from. This prepends the 'same-as-spl' specifier to our configurable boot-order to make this the default behaviour. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: spl: rk3399: implement chip-specific board_spl_was_booted_from()Philipp Tomsich
To support the new "same-as-spl" specifier in the boot-order on the RK3399, this implements the chip-specific mapping from the information obtainable from the BROM to a OF path name. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: spl: support a 'same-as-spl'-specifier in the spl-boot-orderPhilipp Tomsich
It is often desirable to configure the spl-boot-order (i.e. the order that SPL probes devices to find the FIT image containing a full U-Boot) such that it contains 'the same device the SPL stage was booted from' early on. To support this, we introduce the 'same-as-spl' specifier for the spl-boot-order property. This commit adds: - documentation for the new board_spl_was_booted_from() function that individual SoCs/boards should provide, if they can determine where the SPL was booted from - implements the new board_spl_was_booted_from() stub function - adds support for handling the 'same-as-spl' specifier and calling into the per-SoC/per-board support code. This also updates the documentation for the 'u-boot,spl-boot-order' property. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: spl: add documentation for spl_node_to_boot_device()Philipp Tomsich
In the expectation that the spl-boot-order code will eventually gain use outside of mach-rockchip: let's add documentation on the spl_node_to_boot_device() function, which is likely to become a publicly exported function. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: bootrom: add definitions to retrieve BROM boot-sourcePhilipp Tomsich
The Rockchip BROM allows reading where it booted from from SRAM. This adds the necessary definitions (as received from Kever) for the location of this information in the RK3399's SRAM and naming for the constants used. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: rk3399: make spl_board_init board-specificPhilipp Tomsich
The later-stage spl_board_init (as opposed to board_init_f) should set up board-specific details: these differ between the EVB-RK3399 and the RK3399-Q7 (Puma). This moves spl_board_init back into the individual boards and removes the unneeded functionality from Puma. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk322x: update the sysreg number for boot modeKever Yang
The boot mode for rk322x is stored in sysreg 0, update it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: dts: rk3328-evb: add i2c1 and rk805 nodesElaine Zhang
add i2c1 and rk805 nodes to support rk805 init setting. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rk3288: vyasa: Add TPL supportJagan Teki
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288, it is not possible add new SPL features like Falcon mode or etc. So add TPL stage so-that adding new features to SPL is possible. - TPL: DRAM init, clocks - SPL: MMC, falcon, etc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01armv7: rk3288: Move configure_l2ctlr to commonJagan Teki
configure_l2ctlr will be shared between SPL and TPL so move them into asm/arch/sys_proto.h Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01armv7: Move L2CTLR read/write to commonJagan Teki
L2CTLR read/write functions are common to armv7 so, move them in to include/asm/armv7.h and use them where ever it need. Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Backed out the change to arch/arm/mach-tegra/cache.c:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3036: fix grf macro defineKever Yang
Some of macros definition are not correct, fix them according to TRM. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3399: spl: convert to using BOOT_DEVICE_BOOTROMPhilipp Tomsich
Instead of directly calling into the back-to-bootrom code, the RK3399 common SPL implementation now uses BOOT_DEVICE_BOOTROM to trigger a transfer back into the bootrom. With this factored out, the spl_board_init function can not be customised for each RK3399 board. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-01rockchip: dts: rk3229: remove dram channel infoKever Yang
The dram channel info will be auto detect by the driver, we do not need it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-10-01rockchip: rk322x: add sdram driverKever Yang
Add driver for rk322x to support sdram initialize in SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3328: move sdram driver to driver/ramKever Yang
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3288: move sdram driver to driver/ramKever Yang
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3188: move sdram driver to driver/ramKever Yang
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: rk3399: move sdram driver to driver/ramKever Yang
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: imply ADC and SARADC_ROCKCHIP for Rockchip SOCsPhilipp Tomsich
Enable the Rockchip SARADC driver for all Rockchip SoCs. Note that the SARADC peripheral is available on all SoCs except the RK3036 and RK3228. However, as this is a DM-driver, enabling by default will not cause any function problems (and can always be changed from defconfig, if size is a concern). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: David Wu <david.wu@rock-chips.com>
2017-10-01rockchip: dts: Enable SARADC for rk3399-evbDavid Wu
Enable the SARADC for download key pressed detect. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: dts: Enable SARADC for rk3368-sheepDavid Wu
Enable the SARADC for download key pressed detect. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: dts: Enable SARADC for rk3368-px5-evbDavid Wu
Enable the SARADC for download key pressed detect. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: dts: Enable SARADC for rk3328-evbDavid Wu
Enable the SARADC for download key pressed detect. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: dts: Enable SARADC for rk3288-popmetalDavid Wu
Enable the SARADC for download key pressed detect. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: dts: Enable SARADC for rv1108-evbDavid Wu
Enable the SARADC for download key pressed detect. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: dts: rv1108: Add SARADC node at dtsi levelDavid Wu
Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: clk: Add rk3368 SARADC clock supportDavid Wu
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-10-01rockchip: clk: Add rv1108 SARADC clock supportDavid Wu
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-29arm: dts: omap3: sync DTS with Linux 4.14-rc1Karthik Tummala
This re-syncs omap3 DTS file with current file from Linux v4.14-rc1 to ensure a consistent configuration. Upstream Linux removed the redundant Interrupt-parent property from usbhsohci, usbhsehci, ssi_port1 and ssi_port2 sub nodes. Signed-off-by: Karthik Tummala <karthik@techveda.org>
2017-09-29ARM: dts: OMAP5+: Enable all gpios in SPLLokesh Vutla
With DM enabled, gpio numbering is assigned based on the probed order of gpios, irrespective of the gpio base. So enable all necessary gpios in SPL. Fixes: edf25d94d55c (“ARM: dts: OMAP5+: Enable gpio in SPL”) Reported-by: Gou, Hongmei <h-gou@ti.com> Tested-by: Aparna Balasubramanian <aparnab@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-09-29arm: am33xx: security: adds auth support for encrypted imagesMadan Srinivas
This patch adds support for authentication of both plain text and encrypted binaries. A new SECDEV package is needed to enable encryption of binaries by default for AM3x. The ROM authentication API detects encrypted images at runtime and automatically decrypts the image if the signature verification passes. Addition of encryption on AM3x results in a change in the image format. On AM4x, AM5x and, on AM3x devices signing clear test images, the signature is appended to the end of the binary. On AM3x, when the SECDEV package is used to create signed and encrypted images, the signature is added as a header to the start of the binary. So the binary size calculation has been updated to reflect this change. The signing tools and encrypted image format for AM3x cannot be changed to behave like AM4x and AM5x to maintain backward compatibility with older Sitara M-Shield releases. Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
2017-09-29ARM: omap3: am3517-evm: Add device tree and DM supportAdam Ford
With the device tree ported from Linux 4.13, this enables Driver Model and Device Tree support for the am3517-evm Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
2017-09-29arm: dts: am3517_evm: Sync DTS files with Linux 4.13-RC5Adam Ford
To keep the DTS and DTSI files clean and in sync with Linux, new u-boot.dtsi files are added. There are some spacing issues in the patch, but they appear to be present in the Linux source files. I'll try to get to fixing them there, and do a future re-sync at a later date. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
2017-09-29TI: ARCH_OMAP2PLUS: Enable SPL_STACK_R and provide default valueTom Rini
On ARCH_OMAP2PLUS platforms we know what the DDR layout is going to be, and that it is safe to use SPL_STACK_R and provide a default value for it. select this and re-sync the defconfigs. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29ARM: da850-evm: Enable DM_I2CAdam Ford
With DM now enabled with the device tree pulled from Linux, we can enable DM_I2C in U-Boot. Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Add DM_I2C_COMPAT to da850_am18xxevm to fix warning] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-09-29arm: dts: da850: Migrate da850-evm DTS files from Linux 4.13-RC5Adam Ford
A few small additional items are needed to support DM_SPI and DM_SERIAL, so those were added to da850-evm-u-boot.dtsi Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-28nds32: Fix io.h warning message about readbrick
It is caused from asm/io.h declare different input type. Signed-off-by: rick <rick@andestech.com>
2017-09-26arm: mvebu: fix boot from UART on ClearFog BaseBaruch Siach
The ClearFog Base boot from UART when setting the DIP switches to 01001. Unfortunately, the SPL code sometimes fails to detect the UART boot method at run-time. Add an alternative SAR UART boot value to fix this. Note that this alternative value is not documented (Armada 38x Hardware Specifications, Table 48). But experimentations showed it on the ClearFog Base. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: handle unused DRAM banks with ECC enabledChris Packham
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not work because mvebu_sdram_bs() returns 0 and the code was subtracting 1 before checking the size. Remove the -1 from the bank size and the +1 from the total which will skip unused banks and still calculate the correct size. Put the -1 where it is needed for scrubbing via the xor engine. Reported-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: add SAR frequency values for 1.8/2.0GHzChris Packham
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these variants to the sar_freq_tab. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: add additional information to board_add_ram_info()Joshua Scott
Display more information about the current RAM configuration. With these changes the output on a 88F6820 board is SoC: MV88F6820-A0 at 1600 MHz DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled) Signed-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: Add SoC IDs for Marvell's integrated CPUsChris Packham
These SoCs are network packet processors (switch chips) with integrated ARMv7 cores. They share a great deal of commonality with the Armada-XP CPUs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2017-09-26ARM: mvebu: Convert CONFIG_MVNETA to KconfigChris Packham
This converts the following to Kconfig: CONFIG_MVNETA Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 16:03:42 +0000