From 76872bd8fa62e86a804c758584fc7eb774b67390 Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Tue, 30 Jan 2018 08:48:45 +0100 Subject: arm64: dts: rockchip: add OPPs for rk3368-lion This adds CPU operation points for the RK3368. We only add them to the the RK3368-uQ7 SoM (Lion) because patches for the SoC where reverted in the past. commit 6354a06cbaa8 ("Revert "arm64: dts: rockchip: Add basic cpu frequencies for RK3368"") Signed-off-by: Klaus Goger Series-to: linux-rockchip@lists.infradead.org Series-cc: Heiko Stuebner Series-cc: Rob Herring Series-cc: Mark Rutland Series-cc: linux-kernel@vger.kernel.org Cover-letter: add RK3368-uQ7 SoM This patch series adds devicetree files for Theobroma Systems RK3368-uQ module and the corresponding evaluation kit baseboard. See https://www.theobroma-systems.com/rk3368-uq7/ for more information about the module and devkit. @Heiko: I added the OPP points I use as a seperate patch so you can decide if you want to merge it or not as i noticed your reverts in the last cycle. END --- arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 96 ++++++++++++++++++++++++--- 1 file changed, 88 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi index 72be1ae0854f..881f0b44c5b5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -11,6 +11,70 @@ stdout-path = "serial0:115200n8"; }; + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1350000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <975000 975000 1350000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000 1050000 1350000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1150000 1150000 1350000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1300000 1300000 1350000>; + turbo-mode; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1300000 1300000 1350000>; + turbo-mode; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1350000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1025000 1025000 1350000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1125000 1125000 1350000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000 1225000 1350000>; + }; + }; + ext_gmac: gmac-clk { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -239,36 +303,52 @@ status = "okay"; }; -&cpu_l0 { +&cpu_b0 { + clocks = <&cru ARMCLKB>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster0_opp>; }; -&cpu_l1 { +&cpu_b1 { + clocks = <&cru ARMCLKB>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster0_opp>; }; -&cpu_l2 { +&cpu_b2 { + clocks = <&cru ARMCLKB>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster0_opp>; }; -&cpu_l3 { +&cpu_b3 { + clocks = <&cru ARMCLKB>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster0_opp>; }; -&cpu_b0 { +&cpu_l0 { + clocks = <&cru ARMCLKL>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster1_opp>; }; -&cpu_b1 { +&cpu_l1 { + clocks = <&cru ARMCLKL>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster1_opp>; }; -&cpu_b2 { +&cpu_l2 { + clocks = <&cru ARMCLKL>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster1_opp>; }; -&cpu_b3 { +&cpu_l3 { + clocks = <&cru ARMCLKL>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster1_opp>; }; &pinctrl { -- cgit v1.2.3