menu "Target options" config BR2_ARCH_IS_64 bool config BR2_KERNEL_64_USERLAND_32 bool config BR2_SOFT_FLOAT bool config BR2_ARCH_HAS_MMU_MANDATORY bool config BR2_ARCH_HAS_MMU_OPTIONAL bool choice prompt "Target Architecture" default BR2_i386 help Select the target architecture family to build for. config BR2_arcle bool "ARC (little endian)" select BR2_ARCH_HAS_MMU_MANDATORY help Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs that can be used from deeply embedded to high performance host applications. Little endian. config BR2_arceb bool "ARC (big endian)" select BR2_ARCH_HAS_MMU_MANDATORY help Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs that can be used from deeply embedded to high performance host applications. Big endian. config BR2_arm bool "ARM (little endian)" # MMU support is set by the subarchitecture file, arch/Config.in.arm help ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. Little endian. http://www.arm.com/ http://en.wikipedia.org/wiki/ARM config BR2_armeb bool "ARM (big endian)" # MMU support is set by the subarchitecture file, arch/Config.in.arm help ARM is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. Big endian. http://www.arm.com/ http://en.wikipedia.org/wiki/ARM config BR2_aarch64 bool "AArch64 (little endian)" select BR2_ARCH_IS_64 select BR2_ARCH_HAS_MMU_MANDATORY help Aarch64 is a 64-bit architecture developed by ARM Holdings. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php http://en.wikipedia.org/wiki/ARM config BR2_aarch64_be bool "AArch64 (big endian)" select BR2_ARCH_IS_64 select BR2_ARCH_HAS_MMU_MANDATORY help Aarch64 is a 64-bit architecture developed by ARM Holdings. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php http://en.wikipedia.org/wiki/ARM config BR2_csky bool "csky" select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT select BR2_ARCH_HAS_MMU_MANDATORY help csky is processor IP from china. http://www.c-sky.com/ http://www.github.com/c-sky config BR2_i386 bool "i386" select BR2_ARCH_HAS_MMU_MANDATORY help Intel i386 architecture compatible microprocessor http://en.wikipedia.org/wiki/I386 config BR2_m68k bool "m68k" # MMU support is set by the subarchitecture file, arch/Config.in.m68k help Motorola 68000 family microprocessor http://en.wikipedia.org/wiki/M68k config BR2_microblazeel bool "Microblaze AXI (little endian)" select BR2_ARCH_HAS_MMU_MANDATORY help Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus based architecture (little endian) http://www.xilinx.com http://en.wikipedia.org/wiki/Microblaze config BR2_microblazebe bool "Microblaze non-AXI (big endian)" select BR2_ARCH_HAS_MMU_MANDATORY help Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus based architecture (non-AXI, big endian) http://www.xilinx.com http://en.wikipedia.org/wiki/Microblaze config BR2_mips bool "MIPS (big endian)" select BR2_ARCH_HAS_MMU_MANDATORY help MIPS is a RISC microprocessor from MIPS Technologies. Big endian. http://www.mips.com/ http://en.wikipedia.org/wiki/MIPS_Technologies config BR2_mipsel bool "MIPS (little endian)" select BR2_ARCH_HAS_MMU_MANDATORY help MIPS is a RISC microprocessor from MIPS Technologies. Little endian. http://www.mips.com/ http://en.wikipedia.org/wiki/MIPS_Technologies config BR2_mips64 bool "MIPS64 (big endian)" select BR2_ARCH_IS_64 select BR2_ARCH_HAS_MMU_MANDATORY help MIPS is a RISC microprocessor from MIPS Technologies. Big endian. http://www.mips.com/ http://en.wikipedia.org/wiki/MIPS_Technologies config BR2_mips64el bool "MIPS64 (little endian)" select BR2_ARCH_IS_64 select BR2_ARCH_HAS_MMU_MANDATORY help MIPS is a RISC microprocessor from MIPS Technologies. Little endian. http://www.mips.com/ http://en.wikipedia.org/wiki/MIPS_Technologies config BR2_nds32 bool "nds32" select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT select BR2_ARCH_HAS_MMU_MANDATORY help nds32 is a 32-bit architecture developed by Andes Technology. https://en.wikipedia.org/wiki/Andes_Technology config BR2_nios2 bool "Nios II" select BR2_ARCH_HAS_MMU_MANDATORY help Nios II is a soft core processor from Altera Corporation. http://www.altera.com/ http://en.wikipedia.org/wiki/Nios_II config BR2_or1k bool "OpenRISC" select BR2_ARCH_HAS_MMU_MANDATORY help OpenRISC is a free and open processor for embedded system. http://openrisc.io config BR2_powerpc bool "PowerPC" select BR2_ARCH_HAS_MMU_MANDATORY help PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance. Big endian. http://www.power.org/ http://en.wikipedia.org/wiki/Powerpc config BR2_powerpc64 bool "PowerPC64 (big endian)" select BR2_ARCH_IS_64 select BR2_ARCH_HAS_MMU_MANDATORY help PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance. Big endian. http://www.power.org/ http://en.wikipedia.org/wiki/Powerpc config BR2_powerpc64le bool "PowerPC64 (little endian)" select BR2_ARCH_IS_64 select BR2_ARCH_HAS_MMU_MANDATORY help PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance. Little endian. http://www.power.org/ http://en.wikipedia.org/wiki/Powerpc config BR2_riscv bool "RISCV" select BR2_ARCH_HAS_MMU_MANDATORY select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 help RISC-V is an open, free Instruction Set Architecture created by the UC Berkeley Architecture Research group and supported and promoted by RISC-V Foundation. https://riscv.org/ https://en.wikipedia.org/wiki/RISC-V config BR2_sh bool "SuperH" select BR2_ARCH_HAS_MMU_OPTIONAL help SuperH (or SH) is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Hitachi. http://www.hitachi.com/ http://en.wikipedia.org/wiki/SuperH config BR2_sparc bool "SPARC" select BR2_ARCH_HAS_MMU_MANDATORY help SPARC (from Scalable Processor Architecture) is a RISC instruction set architecture (ISA) developed by Sun Microsystems. http://www.oracle.com/sun http://en.wikipedia.org/wiki/Sparc config BR2_sparc64 bool "SPARC64" select BR2_ARCH_IS_64 select BR2_ARCH_HAS_MMU_MANDATORY help SPARC (from Scalable Processor Architecture) is a RISC instruction set architecture (ISA) developed by Sun Microsystems. http://www.oracle.com/sun http://en.wikipedia.org/wiki/Sparc config BR2_x86_64 bool "x86_64" select BR2_ARCH_IS_64 select BR2_ARCH_HAS_MMU_MANDATORY help x86-64 is an extension of the x86 instruction set (Intel i386 architecture compatible microprocessor). http://en.wikipedia.org/wiki/X86_64 config BR2_xtensa bool "Xtensa" # MMU support is set by the subarchitecture file, arch/Config.in.xtensa help Xtensa is a Tensilica processor IP architecture. http://en.wikipedia.org/wiki/Xtensa http://www.tensilica.com/ endchoice # For some architectures or specific cores, our internal toolchain # backend is not suitable (like, missing support in upstream gcc, or # no ChipCo fork exists...) config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT bool config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT bool default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT # The following symbols are selected by the individual # Config.in.$ARCH files config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8 bool config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 bool select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8 config BR2_ARCH_NEEDS_GCC_AT_LEAST_5 bool select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 config BR2_ARCH_NEEDS_GCC_AT_LEAST_6 bool select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 config BR2_ARCH_NEEDS_GCC_AT_LEAST_7 bool select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 config BR2_ARCH_NEEDS_GCC_AT_LEAST_8 bool select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 # The following string values are defined by the individual # Config.in.$ARCH files config BR2_ARCH string config BR2_ENDIAN string config BR2_GCC_TARGET_ARCH string config BR2_GCC_TARGET_ABI string config BR2_GCC_TARGET_NAN string config BR2_GCC_TARGET_FP32_MODE string config BR2_GCC_TARGET_CPU string # The value of this option will be passed as --with-fpu= when # building gcc (internal backend) or -mfpu= in the toolchain # wrapper (external toolchain) config BR2_GCC_TARGET_FPU string # The value of this option will be passed as --with-float= when # building gcc (internal backend) or -mfloat-abi= in the toolchain # wrapper (external toolchain) config BR2_GCC_TARGET_FLOAT_ABI string # The value of this option will be passed as --with-mode= when # building gcc (internal backend) or -m in the toolchain # wrapper (external toolchain) config BR2_GCC_TARGET_MODE string # Must be selected by binary formats that support shared libraries. config BR2_BINFMT_SUPPORTS_SHARED bool # Must match the name of the architecture from readelf point of view, # i.e the "Machine:" field of readelf output. See get_machine_name() # in binutils/readelf.c for the list of possible values. config BR2_READELF_ARCH_NAME string # Set up target binary format choice prompt "Target Binary Format" default BR2_BINFMT_ELF if BR2_USE_MMU default BR2_BINFMT_FLAT config BR2_BINFMT_ELF bool "ELF" depends on BR2_USE_MMU select BR2_BINFMT_SUPPORTS_SHARED help ELF (Executable and Linkable Format) is a format for libraries and executables used across different architectures and operating systems. config BR2_BINFMT_FLAT bool "FLAT" depends on !BR2_USE_MMU help FLAT binary is a relatively simple and lightweight executable format based on the original a.out format. It is widely used in environment where no MMU is available. endchoice # Set up flat binary type choice prompt "FLAT Binary type" default BR2_BINFMT_FLAT_ONE depends on BR2_BINFMT_FLAT config BR2_BINFMT_FLAT_ONE bool "One memory region" help All segments are linked into one memory region. config BR2_BINFMT_FLAT_SHARED bool "Shared binary" depends on BR2_m68k # Even though this really generates shared binaries, there is no libdl # and dlopen() cannot be used. So packages that require shared # libraries cannot be built. Therefore, we don't select # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS. # Although this adds -static to the compilation, that's not a problem # because the -mid-shared-library option overrides it. help Allow to load and link indiviual FLAT binaries at run time. endchoice if BR2_arcle || BR2_arceb source "arch/Config.in.arc" endif if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be source "arch/Config.in.arm" endif if BR2_csky source "arch/Config.in.csky" endif if BR2_m68k source "arch/Config.in.m68k" endif if BR2_microblazeel || BR2_microblazebe source "arch/Config.in.microblaze" endif if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el source "arch/Config.in.mips" endif if BR2_nds32 source "arch/Config.in.nds32" endif if BR2_nios2 source "arch/Config.in.nios2" endif if BR2_or1k source "arch/Config.in.or1k" endif if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le source "arch/Config.in.powerpc" endif if BR2_riscv source "arch/Config.in.riscv" endif if BR2_sh source "arch/Config.in.sh" endif if BR2_sparc || BR2_sparc64 source "arch/Config.in.sparc" endif if BR2_i386 || BR2_x86_64 source "arch/Config.in.x86" endif if BR2_xtensa source "arch/Config.in.xtensa" endif endmenu # Target options