From 9b3d52b4008abacc4ea4867e0fe4e68ed32b1920 Mon Sep 17 00:00:00 2001 From: Mark Corbin Date: Wed, 12 Sep 2018 11:22:54 +0100 Subject: arch: add support for RISC-V 64-bit (riscv64) architecture This enables a riscv64 system to be built with a Buildroot generated toolchain (gcc >= 7.x, binutils >= 2.30, glibc only). This configuration has been used to successfully build a qemu-bootable riscv-linux-4.15 kernel (https://github.com/riscv/riscv-linux.git). Signed-off-by: Mark Corbin [Thomas: - simplify arch.mk.riscv by directly setting GCC_TARGET_ARCH - simplify glibc.mk changes by using GLIBC_CONF_ENV.] Signed-off-by: Thomas Petazzoni --- arch/Config.in | 15 ++++++++ arch/Config.in.riscv | 102 +++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arch.mk.riscv | 28 ++++++++++++++ 3 files changed, 145 insertions(+) create mode 100644 arch/Config.in.riscv create mode 100644 arch/arch.mk.riscv (limited to 'arch') diff --git a/arch/Config.in b/arch/Config.in index 7d1aeb2174..8bd57fe1cc 100644 --- a/arch/Config.in +++ b/arch/Config.in @@ -198,6 +198,17 @@ config BR2_powerpc64le http://www.power.org/ http://en.wikipedia.org/wiki/Powerpc +config BR2_riscv + bool "RISCV" + select BR2_ARCH_HAS_MMU_MANDATORY + select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 + help + RISC-V is an open, free Instruction Set Architecture created + by the UC Berkeley Architecture Research group and supported + and promoted by RISC-V Foundation. + https://riscv.org/ + https://en.wikipedia.org/wiki/RISC-V + config BR2_sh bool "SuperH" select BR2_ARCH_HAS_MMU_OPTIONAL @@ -423,6 +434,10 @@ if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le source "arch/Config.in.powerpc" endif +if BR2_riscv +source "arch/Config.in.riscv" +endif + if BR2_sh source "arch/Config.in.sh" endif diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv new file mode 100644 index 0000000000..4361890bf4 --- /dev/null +++ b/arch/Config.in.riscv @@ -0,0 +1,102 @@ +# RISC-V CPU ISA extensions. + +config BR2_RISCV_ISA_RVI + bool + +config BR2_RISCV_ISA_RVM + bool + +config BR2_RISCV_ISA_RVA + bool + +config BR2_RISCV_ISA_RVF + bool + +config BR2_RISCV_ISA_RVD + bool + +config BR2_RISCV_ISA_RVC + bool + +choice + prompt "Target Architecture Variant" + default BR2_riscv_g + +config BR2_riscv_g + bool "General purpose (G)" + select BR2_RISCV_ISA_RVI + select BR2_RISCV_ISA_RVM + select BR2_RISCV_ISA_RVA + select BR2_RISCV_ISA_RVF + select BR2_RISCV_ISA_RVD + help + General purpose (G) is equivalent to IMAFD. + +config BR2_riscv_custom + bool "Custom architecture" + select BR2_RISCV_ISA_RVI + select BR2_RISCV_ISA_CUSTOM_RVA + +endchoice + +if BR2_riscv_custom + +comment "Instruction Set Extensions" + +config BR2_RISCV_ISA_CUSTOM_RVM + bool "Integer Multiplication and Division (M)" + select BR2_RISCV_ISA_RVM + +config BR2_RISCV_ISA_CUSTOM_RVA + bool "Atomic Instructions (A)" + select BR2_RISCV_ISA_RVA + +config BR2_RISCV_ISA_CUSTOM_RVF + bool "Single-precision Floating-point (F)" + select BR2_RISCV_ISA_RVF + +config BR2_RISCV_ISA_CUSTOM_RVD + bool "Double-precision Floating-point (D)" + depends on BR2_RISCV_ISA_RVF + select BR2_RISCV_ISA_RVD + +config BR2_RISCV_ISA_CUSTOM_RVC + bool "Compressed Instructions (C)" + select BR2_RISCV_ISA_RVC +endif + +config BR2_RISCV_64 + bool + default y + select BR2_ARCH_IS_64 + +choice + prompt "Target ABI" + default BR2_RISCV_ABI_LP64 + +config BR2_RISCV_ABI_LP64 + bool "lp64" + depends on BR2_ARCH_IS_64 + +config BR2_RISCV_ABI_LP64F + bool "lp64f" + depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF + +config BR2_RISCV_ABI_LP64D + bool "lp64d" + depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD +endchoice + +config BR2_ARCH + default "riscv64" if BR2_ARCH_IS_64 + +config BR2_ENDIAN + default "LITTLE" + +config BR2_GCC_TARGET_ABI + default "lp64" if BR2_RISCV_ABI_LP64 + default "lp64f" if BR2_RISCV_ABI_LP64F + default "lp64d" if BR2_RISCV_ABI_LP64D + +config BR2_READELF_ARCH_NAME + default "RISC-V" diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv new file mode 100644 index 0000000000..022d1a6809 --- /dev/null +++ b/arch/arch.mk.riscv @@ -0,0 +1,28 @@ +# +# Configure the GCC_TARGET_ARCH variable and append the +# appropriate RISC-V ISA extensions. +# + +ifeq ($(BR2_riscv),y) + +ifeq ($(BR2_ARCH_IS_64),y) +GCC_TARGET_ARCH := rv64i +endif + +ifeq ($(BR2_RISCV_ISA_RVM),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m +endif +ifeq ($(BR2_RISCV_ISA_RVA),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a +endif +ifeq ($(BR2_RISCV_ISA_RVF),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f +endif +ifeq ($(BR2_RISCV_ISA_RVD),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d +endif +ifeq ($(BR2_RISCV_ISA_RVC),y) +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c +endif + +endif -- cgit v1.2.3