From 0c12a1592c49c4fccea1df3eac9bf769aa1bd503 Mon Sep 17 00:00:00 2001 From: vijay rai Date: Tue, 15 Apr 2014 11:34:12 +0530 Subject: powerpc/85xx: Enhance get_sys_info() to check clocking mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain Signed-off-by: Vijay Rai Reviewed-by: York Sun --- include/e500.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/e500.h') diff --git a/include/e500.h b/include/e500.h index 0c2432657b..5884a224d2 100644 --- a/include/e500.h +++ b/include/e500.h @@ -24,6 +24,9 @@ typedef struct #ifdef CONFIG_SYS_DPAA_PME unsigned long freq_pme; #endif +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + unsigned char diff_sysclk; +#endif } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ -- cgit v1.2.3