From b2893e1fcb28fad8c8b317104df8cee0142c7631 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 5 Nov 2007 09:34:06 -0600 Subject: 83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the currently-defined 83xx boards. This change guarantees that the environment will be located on the first flash sector after the U-Boot image. Signed-off-by: Timur Tabi Signed-off-by: Kim Phillips --- include/configs/MPC8313ERDB.h | 3 ++- include/configs/MPC8323ERDB.h | 5 +++-- include/configs/MPC832XEMDS.h | 5 +++-- include/configs/MPC8349EMDS.h | 2 +- include/configs/MPC8349ITX.h | 3 ++- include/configs/MPC8360EMDS.h | 5 +++-- 6 files changed, 14 insertions(+), 9 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 6568fe13b8..0c3bc16c9c 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -178,6 +178,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -326,7 +327,7 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 376973b94d..558f94bb77 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -116,6 +116,7 @@ #undef CFG_RAMBOOT #endif +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ @@ -354,8 +355,8 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index c9c6d88cf0..5345fc62f8 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -145,6 +145,7 @@ #undef CFG_RAMBOOT #endif +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ @@ -410,8 +411,8 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 92555bac42..7d5b17b50b 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -456,7 +456,7 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 54cab528bd..2a2e753c87 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -261,6 +261,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ @@ -404,8 +405,8 @@ boards, we say we have two, but don't display a message if we find only one. */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 41f062ce72..8098951c5b 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -170,6 +170,7 @@ #undef CFG_RAMBOOT #endif +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ @@ -443,8 +444,8 @@ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x20000 #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ -- cgit v1.2.3 From 19580e660cc8da49f16536a8bd78c047c7bc12e5 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 18 Sep 2007 12:37:57 +0800 Subject: mpc83xx: Add the support of MPC837xEMDS board The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu --- include/configs/MPC837XEMDS.h | 605 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 605 insertions(+) create mode 100644 include/configs/MPC837XEMDS.h (limited to 'include/configs') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h new file mode 100644 index 0000000000..7e344925ce --- /dev/null +++ b/include/configs/MPC837XEMDS.h @@ -0,0 +1,605 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Dave Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC837X 1 /* MPC837X CPU specific */ +#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66MHz, then + * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_6X1 |\ + HRCWL_CORE_TO_CSB_1_5X1) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LDP_CLEAR) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LDP_CLEAR) +#endif + +/* + * eTSEC Clock Config + */ +#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ +#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ + +/* + * System IO Config + */ +#define CFG_SICRH 0x00000000 +#define CFG_SICRL 0x00000000 + +/* + * Output Buffer Impedance + */ +#define CFG_OBIR 0x31100000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CFG_83XX_DDR_USES_CS0 +#define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ + +#undef CONFIG_DDR_ECC /* support DDR ECC function */ +#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ + +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ + +#if defined(CONFIG_SPD_EEPROM) +#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ +#else +/* + * Manually set up DDR parameters + * WHITE ELECTRONIC DESGGNS - W3HG64M72EEU403PD4 SO-DIMM + * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 + */ +#define CFG_DDR_SIZE 512 /* MB */ +#define CFG_DDR_CS0_BNDS 0x0000001f +#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ + | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) + /* 0x80010202 */ +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00620802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | (13 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x3935d322 */ +#define CFG_DDR_TIMING_2 ( ( 2 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x231088c8 */ +#define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x03E00100 */ +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CFG_DDR_MODE ( ( 0x0450 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) + /* ODT 150ohm CL=3, AL=2 on SDRAM */ +#define CFG_DDR_MODE2 0x00000000 +#endif + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00040000 /* memtest region */ +#define CFG_MEMTEST_END 0x00140000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* + * BCSR on the Local Bus + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ + +#define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + +/* + * NAND Flash on the Local Bus + */ +#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CFG_BR3_PRELIM ( CFG_NAND_BASE \ + | (2< " +#endif + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_HAS_BD_T 1 +#define CONFIG_OF_HAS_UBOOT_ENV 1 + +#define OF_CPU "PowerPC,837x@0" +#define OF_SOC "soc837x@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc837x@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + +#ifdef CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ +#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#endif /* CONFIG_PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC1" + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_SDRAM_LOWER CFG_SDRAM_BASE +#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) + +#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* BCSR: cache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:00:83:79 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc837xemds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 921d4b19ad1be704df58725485d9292dc0414adf Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Mon, 19 Nov 2007 12:30:09 -0600 Subject: mpc83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions for 837x Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x. This change guarantees that the environment will be located on the first flash sector after the U-Boot image. Signed-off-by: Kim Phillips --- include/configs/MPC837XEMDS.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/configs') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 7e344925ce..524ff7c928 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -197,6 +197,7 @@ #undef CFG_RAMBOOT #endif +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -386,7 +387,7 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else -- cgit v1.2.3 From e6af9932d31171e35db880e7b2f29f903b1b7660 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 26 Nov 2007 11:00:54 -0600 Subject: Remove CONFIG options related to OF that we dont use The MPC8360E MDS config defined: CONFIG_OF_HAS_BD_T CONFIG_OF_HAS_UBOOT_ENV Which we don't use or ever needed. This seems like copy-paste feature creep. Signed-off-by: Kumar Gala --- include/configs/MPC8360EMDS.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 8098951c5b..c192f33658 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -349,8 +349,6 @@ #define CONFIG_OF_LIBFDT 1 #undef CONFIG_OF_FLAT_TREE #define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_HAS_BD_T 1 -#define CONFIG_OF_HAS_UBOOT_ENV 1 #define OF_CPU "PowerPC,8360@0" #define OF_SOC "soc8360@e0000000" -- cgit v1.2.3 From a1e1ac849249310e5e2e5c7148e9fb353a8317a7 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 20 Dec 2007 01:30:48 -0600 Subject: mpc83xx: Remove CONFIG options related to OF that we dont use (on 837x) continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x Signed-off-by: Kim Phillips --- include/configs/MPC837XEMDS.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 524ff7c928..772fd02381 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -297,8 +297,6 @@ /* Pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_HAS_BD_T 1 -#define CONFIG_OF_HAS_UBOOT_ENV 1 #define OF_CPU "PowerPC,837x@0" #define OF_SOC "soc837x@e0000000" -- cgit v1.2.3 From e496865ecc31a2fe2f9abfe798334bb02aaf05ab Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Thu, 20 Dec 2007 12:58:51 -0500 Subject: sbc8349: enable libfdt by default on WRS SBC8349 board. Make libfdt the default for the WRS SBC8349 board. Parallel of commit 35cc4e4823668e8745854899cfaedd4489beb0ef done for the other 83xx based boards. Also fix a typo in CONFIG_PCI. Signed-off-by: Paul Gortmaker --- include/configs/sbc8349.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/configs') diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e7d8a5a662..45f20dc12c 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -310,7 +310,7 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #define OF_CPU "PowerPC,8349@0" @@ -458,7 +458,7 @@ #define CONFIG_CMD_PING #if defined(CONFIG_PCI) - #define CONFG_CMD_PCI + #define CONFIG_CMD_PCI #endif #if defined(CFG_RAMBOOT) -- cgit v1.2.3 From 5b8bc606c61456566af6912f818a153b6b06f242 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 20 Dec 2007 14:09:22 -0600 Subject: mpc83xx: convert to using do_fixup_*() convert to using simpler mpc85xx style fdt update code; streamline by eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm the old school FLAT_TREE code from 83xx (since the sbc8349 was just converted over to using libfdt). Signed-off-by: Kim Phillips --- include/configs/MPC8313ERDB.h | 6 +----- include/configs/MPC8323ERDB.h | 7 +------ include/configs/MPC832XEMDS.h | 7 +------ include/configs/MPC8349EMDS.h | 6 +----- include/configs/MPC8349ITX.h | 8 ++------ include/configs/MPC8360EMDS.h | 8 +------- include/configs/MPC837XEMDS.h | 6 +----- include/configs/sbc8349.h | 6 +----- 8 files changed, 9 insertions(+), 45 deletions(-) (limited to 'include/configs') diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 0c3bc16c9c..c9a9c83f22 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -231,11 +231,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8313@0" -#define OF_SOC "soc8313@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * Serial Port diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 558f94bb77..564de02f5b 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -270,12 +270,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8323@0" -#define OF_SOC "soc8323@e0000000" -#define OF_QE "qe@e0100000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 5345fc62f8..a48b3117b6 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -321,12 +321,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8323@0" -#define OF_SOC "soc8323@e0000000" -#define OF_QE "qe@e0100000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 7d5b17b50b..03409bbbaf 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -341,11 +341,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8349@0" -#define OF_SOC "soc8349@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 2a2e753c87..49dc0de535 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -298,12 +298,8 @@ boards, we say we have two, but don't display a message if we find only one. */ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP - -#define OF_CPU "PowerPC,8349@0" -#define OF_SOC "soc8349@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * PCI diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index c192f33658..fedb8a9c5b 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -347,14 +347,8 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 -#undef CONFIG_OF_FLAT_TREE #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8360@0" -#define OF_SOC "soc8360@e0000000" -#define OF_QE "qe@e0100000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 772fd02381..0958e6b967 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -297,11 +297,7 @@ /* Pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,837x@0" -#define OF_SOC "soc837x@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc837x@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 45f20dc12c..9efe3c49de 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -312,11 +312,7 @@ /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8349@0" -#define OF_SOC "soc8349@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ -- cgit v1.2.3