From aa8e00fab5e65a07c2cae52274946a908805ea60 Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Thu, 15 Jan 2015 11:45:56 +0900 Subject: samsung: board: support eMMC reset using DT Some exynos boards require special handling of nRESET_OUT line for eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards. This will support eMMC reset using DT from reset_misc of samsung common board file. Signed-off-by: Joonyoung Shim Signed-off-by: Minkyu Kang --- board/samsung/common/board.c | 28 ++++++++++++++++++++++++++++ board/samsung/odroid/odroid.c | 8 -------- 2 files changed, 28 insertions(+), 8 deletions(-) (limited to 'board/samsung') diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 8b4c8e9a9d..da2245ff9d 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -355,3 +355,31 @@ int misc_init_r(void) return 0; } #endif + +void reset_misc(void) +{ + struct gpio_desc gpio = {}; + int node; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, + "samsung,emmc-reset"); + if (node < 0) + return; + + gpio_request_by_name_nodev(gd->fdt_blob, node, "reset-gpio", 0, &gpio, + GPIOD_IS_OUT); + + if (dm_gpio_is_valid(&gpio)) { + /* + * Reset eMMC + * + * FIXME: Need to optimize delay time. Minimum 1usec pulse is + * required by 'JEDEC Standard No.84-A441' (eMMC) + * document but real delay time is expected to greater + * than 1usec. + */ + dm_gpio_set_value(&gpio, 0); + mdelay(10); + dm_gpio_set_value(&gpio, 1); + } +} diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index e3517f2eb2..306cc0f9d9 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -503,11 +503,3 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } #endif - -void reset_misc(void) -{ - /* Reset eMMC*/ - gpio_set_value(EXYNOS4X12_GPIO_K12, 0); - mdelay(10); - gpio_set_value(EXYNOS4X12_GPIO_K12, 1); -} -- cgit v1.2.3 From b00f8edb5a1a98636afa121c7c8eacc9045ae19f Mon Sep 17 00:00:00 2001 From: Joonyoung Shim Date: Fri, 23 Jan 2015 17:30:07 +0900 Subject: odroid: fix g2d sclk rate G2D core should be provided 200MHz clock rate. Signed-off-by: Joonyoung Shim Signed-off-by: Minkyu Kang --- board/samsung/odroid/odroid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'board/samsung') diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 306cc0f9d9..bff6ac928c 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -248,12 +248,12 @@ static void board_clock_init(void) * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ - set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set); -- cgit v1.2.3