From 49e946cb6ae0448492147ffcb9dcd7d0af1eab4d Mon Sep 17 00:00:00 2001 From: Stephen George Date: Mon, 25 Mar 2013 07:40:12 +0000 Subject: board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M Debug trace buffers are memory mapped in DCSR space beyond 4M. Signed-off-by: Stephen George Signed-off-by: Andy Fleming --- board/freescale/t4qds/tlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/freescale/t4qds/tlb.c') diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index 80eb511e1d..92c01cf95c 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -115,7 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_4M, 1), + 0, 13, BOOKE_PAGESZ_32M, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* -- cgit v1.2.3